so many spelling mistakes.. you could have explained the PPT itself.. and please improve on pronunciations

May I know the course details?

can you please upload remaining part of this project?

Xor

Here is the complete code - " `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: BITS Pilani // Engineer: Narayan // // Create Date: 19.08.2024 23:34:43 // Design Name: Asynchronous FIFO // Module Name: top // Project Name: // Target Devices: // Tool Versions: // Description: // This module implements an Asynchronous FIFO with separate read and write clocks. // It includes logic to handle data synchronization across different clock domains // using Gray code pointers to avoid metastability and synchronization errors. // // Dependencies: None // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module top ( input wr_clk, // Write clock input rd_clk, // Read clock input rst, // Asynchronous reset input wr_en, // Write enable signal input rd_en, // Read enable signal input [7:0] write_data, // Data input for writing to FIFO output reg [7:0] read_data, // Data output for reading from FIFO output wire empty, // Flag to indicate FIFO is empty output wire full // Flag to indicate FIFO is full ); parameter fifo_depth = 8; // FIFO depth is 8, so address pointer will be 3 bits wide parameter add_size = 4; // Address size set to 4 bits to handle full/empty condition // Define the read and write pointers with 4 bits each reg [3:0] wptr, rptr; wire [3:0] wptr_gray, rptr_gray; // FIFO buffer memory of 8 entries, each 8 bits wide reg [7:0] mem [7:0]; // Synchronized write and read pointers (Gray code) reg [3:0] wptr_gray_sync; reg [3:0] wptr_gray_ff1, wptr_gray_ff2; reg [3:0] rptr_gray_sync; reg [3:0] rptr_gray_ff1, rptr_gray_ff2; // Write data into FIFO buffer // This block is triggered by the write clock and checks for write enable and FIFO full conditions always @(posedge wr_clk) begin if (rst) begin // Reset write pointer to zero wptr <= 4'b0000; end else if (wr_en && !full) begin // Write data to the memory at the current write pointer position mem[wptr] <= write_data; // Increment the write pointer wptr <= wptr + 1; end end // Read data from FIFO buffer // This block is triggered by the read clock and checks for read enable and FIFO empty conditions always @(posedge rd_clk) begin if (rst) begin // Reset read pointer to zero rptr <= 4'b0000; end else if (rd_en && !empty) begin // Read data from the memory at the current read pointer position read_data <= mem[rptr]; // Increment the read pointer rptr <= rptr + 1; end end // Convert binary write and read pointers to Gray code // Gray code minimizes the risk of synchronization errors by ensuring only one bit changes at a time assign wptr_gray = wptr ^ (wptr >> 1); assign rptr_gray = rptr ^ (rptr >> 1); // Synchronize the write pointer to the read clock domain // This prevents metastability when comparing pointers across different clock domains always @(posedge rd_clk) begin if (rst) begin // Reset synchronization flip-flops wptr_gray_ff1 <= 0; wptr_gray_ff2 <= 0; wptr_gray_sync <= 0; end else begin // First stage of synchronization wptr_gray_ff1 <= wptr_gray; // Second stage of synchronization wptr_gray_ff2 <= wptr_gray_ff1; // Final synchronized write pointer in read clock domain wptr_gray_sync <= wptr_gray_ff2; end end // Synchronize the read pointer to the write clock domain // This prevents metastability when comparing pointers across different clock domains always @(posedge wr_clk) begin if (rst) begin // Reset synchronization flip-flops rptr_gray_ff1 <= 0; rptr_gray_ff2 <= 0; rptr_gray_sync <= 0; end else begin // First stage of synchronization rptr_gray_ff1 <= rptr_gray; // Second stage of synchronization rptr_gray_ff2 <= rptr_gray_ff1; // Final synchronized read pointer in write clock domain rptr_gray_sync <= rptr_gray_ff2; end end // Calculate the empty condition // The FIFO is empty when the read pointer equals the synchronized write pointer assign empty = (rptr_gray == wptr_gray_sync); // Calculate the full condition // The FIFO is full when the write pointer is one position behind the read pointer, after wrapping around assign full = ((wptr_gray[3] != rptr_gray_sync[3]) && // MSB check to detect wrap-around (wptr_gray[2] == rptr_gray_sync[2]) && // Ensure pointers are aligned except MSB (wptr_gray[1:0] == rptr_gray_sync[1:0])); // Lower bits must match endmodule " if you have any question or want to prepare for an interview @ this project contact me on [email protected]. free of cost guidance. i wrote the entire code on my own, just added the comments by AICheers!!

please share the code mam

2x1 mux output f=x'y' + y'z' 2x4 decoder output f=d(ab' + bc')

explanation is awesome, please provide the copy of code in EDA playground

Mam in reversing the digit question you are using left shift right,so while using left shift we will be appending 0 to the vacant bit right,so how the shifted bit get appending back ,its possible only in bit rotation right

Can you please increase the quality of this video it's not clearly seen

xnor

Thank you so much very helpful...

which overriding is preferred?

What is j ?

Mam Is it free

Please share the pdf

can you please send the part1 video link mam

Full state explaination I'm unable to understand....

Please send Part 1 video link

Sir Testbench for this code ?

Can we use this example in an interview lullzzz ?

Tq mam

Well elucidated ma'am your voice is so sweet

Hi what is the name of faculty ?

Mam can u send link of counties session pls

I think code is from verification guide

Thank you for your explaination. It was very helpful.

Can I get that PDF

Plz make interview question system verilog also mam ,plz

Very helpful videos mam,

Mam, in q.18 option b is correct. Plz correct me if iam wrong

In q.14 ,unit of delay is correct but they didn't mention about any specific time units , So y don't we take (b) option

Mam ,a big thanks for these videos,very helpful for interview preparation

for small Startups or Consultants it is almost impossible to gain advantage of these level of verifications. UVM ans SystemVerilog Assertions cannot be used. there are only a bunch of tools available that cost a fortune, you need a loan to buy a licence. Despite these major issues it is possible to be creative with verification and coverage by using standard code. Usually Universities don't tech that simplified way to help coverage. I've done the SystemVerilog and UVM main specialist course to learn how to validate and verify a digital design, and I never used that stuff to verify my design or at least I never seen company using those advanced Systemverilog stuff.

interested how to apply

Tq mam upload more videos based on protocol also send code pdf

Size of the d_arr1 = 5 Values of d_qrr 1 3 5 7 9 Size of darr2 = 10 Values 1 3 5 7 9 2 4 6 8 10 Size of darr1 equals 0

Thank you very much for this first session. Will the rest of the sessions be uploaded?

Intreseted

How i need to find Live classes

Hi mam, I am really happy with the session and could you please tell me that how to access the PPT....? And thank you in advance mam

Thanku for this workshop .. it is really very helpful .

3rd. XNOR

can u apload remaining week schedule

Hi UART is full duplex protocol, it's not half duplex protocol can you please update your PPT

🎉👏

time line 24:00 we can't use for loop and increment is not possible in constraints right

Nice explanation 😊