Hi there What about whenever clk enable clock is just one cycle capture window? Does it make any sense to add timing exception? I was deriving a 1200Hz clock enable from 50MHz clock, each 1200Hz pulse width is 1 50MHz cycle intended to capture 1200bps serial data. Thanks in advance

Thanks for the HD vid. The old ones are unreadable.

Looks nice, can you please provide link to possible hardware intel+fpga boards ?

thanks so much, this tutorial really helped me

Is there any way you can upload your presentations in a better display quality? For instance this one, the maximum display is 480p ... is there a reason why this presentation is not available in 720p or better quality? I Thank you very much for your attention and for not turning off comments on this training.

Just an FYI, at around [17:10], your power point has the description for `set_clock_uncertainty` and `derive_clock_uncertainty` reversed. As long as your audience is listening and not looking, they should be fine :P

try c++ signal processing coding (c++ to circuits) instead of vhdl or verilog, its much better than low level design for large code pieces

speak up son

Них*я не понял, но очень интересно

Funny to see such a presentation from Altera while their tools are notoriously unclear about timing, and their datasheet incomplete about it.

You are a multi billion dollar company and you cannot afford videos in HD quality? PM me, I would do that for you!

where can we find these slides ?

where can i get the sr_vista_rot_2x2x25 image

I find gold mine of electronics

Is for gaming?

Thanks for Such an Awesome Video.

Is it a Human Being speaking or a robot?

Thanks Steve =)

480p... I would like to watch it, but I do not see it..

Why are all your videos in such a low resolution?

The link does not seem to be correct anymore. The design can be found here: 01.org/multi-rail-power-sequencer-and-monitor

Well, from this Ad I could presume one can buy this FPGA IP Core to make a better DC-DC converter with monitoring/control and etc. Still, I could not understand, why would they not integrate the DC-DC converters into FPGA crystal and I could just feed 5V vccone and they step-down all the necessary vccio and vddcore programmable. At least for industrial grade MAX-series.

first comment

Intel® is coming back soon in the technological world.

I wrote this comment because I am Intel user.

Intel beat amd ryzen in 2022 I hope that .

I comments this because I hate AMD.

Intel processors need to be made more powerful than amd ryzen processors.

Hyper Mario Brothers

Next: How to avoid Turbo-Lag

I’m sorry but I’m first

kzbin.info/door/kHnngw4Sq29VOpqVTUZWGQ

Is this module is built in the max 10 FPGA ?

intel stepping into "POWER" sector I'm excited/

why there is only 7 views and 0 comments

Hey Intel, I can suggest few changes, that might improve the simulations with Quartus pretty easy.

Quartus Standart or Quartus Lite support?

Please, review Ubuntu 20.04 support for Quartus and SoC EDS.

Hey Intel, please make HLS tool in Quartus lite version free, like vivado.

wow... First comment

woah they're using vyond

my 3 years old kid really liked the video and asked for another one

Another marketing bullshit video. No content there, go along!

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