32:10

One of the best video.

12:36 Dijsktra also finds single source shortest path, i.e., single source multiple destinations. It's just that it might give incorrect result if graph has negative edges.

This is good stuff. Many of these videos are really good and in depth.

58:05 Assuming adjacency list representation: Finding all nodes with no predecessor will take O(|V|+|E|) = O(V^2) in worst case. The simple algo would be to take an array/map of |V| size size and traverse the the adjacency list, and whenver u-> v edge is there, increment map[v] by 1. Finding all nodes with no successor will take O(|V|) time as the algo would be to traverse all |V| directory nodes in adjacency list and simply check if len(list(v)) = 0, or not.

Quite Helpful!!

Thank you so much or the explanation sir. It is digging a deeper perspective .

Anyone have VLSI digital signal processing systems,author of keshab k.parhi,exercise solutions

Is there a recommended text/reference book you've followed for this course?

大學教授提供的參考內容。贊

I didn't understand how to find a critical path

Introduction to Hardware Description Language: kzbin.info/www/bejne/j3q6moqia72NbdU

Such an informative lecture.....

Tabalchi g**nd

Superb

Nice sir 👍👍

good enough

Best explanation & presentation thank you Prof

1st comment: wondering no one done yet

Wonderful Explanation ..

Thank you Sir !

Please do a lecture series on the SODC book by Giovanni Micheli. Will really help us a lot.

Very neatly explained.helped a lot

Hi sir, you are doing well . As i am design verification trainee can please give me lecture about verilog ,system verilog and uvm ... Thanks .

Sir I heard your presentation in VDAT 2019. I want a material for Memory compiler .... If any possibility occur please send me ....

Thank you sir , for putting this wonderful course online

30:00

Thanks for fucking up the audio, at least the video is high resolution and the instructor speaks enjoyable English.

Thank you sir for the course...

Thank you sir for uploading this video.