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Пікірлер
@junmanuelhernandezveloza4294
@junmanuelhernandezveloza4294 Ай бұрын
What is the code?
@Hendershot93
@Hendershot93 Ай бұрын
Well put together sir.
@muhammadaqidajmal7399
@muhammadaqidajmal7399 2 ай бұрын
Xpehe aq
@I_am_Ashok
@I_am_Ashok 2 ай бұрын
Thanks for such an advanced level video lecture. God bless you..
@NatashaStory-p6r
@NatashaStory-p6r 3 ай бұрын
Walker Joseph Harris Sandra Brown Robert
@GaryRichardson-x9x
@GaryRichardson-x9x 3 ай бұрын
White Jose Jackson Sharon Jones Patricia
@Camilink94
@Camilink94 3 ай бұрын
I have no idea why KZbin recommended this
@Prabagaran-s3b
@Prabagaran-s3b 3 ай бұрын
it helps me lot,add more vedio
@SamuelMegan-k4f
@SamuelMegan-k4f 3 ай бұрын
Brown Donald Hernandez John Harris James
@TheCheech0203
@TheCheech0203 4 ай бұрын
You are a legend Dr. Li thank you!!
@GoodWill-s8j
@GoodWill-s8j 5 ай бұрын
It's 2024, you know?
@jomelsagsagat4020
@jomelsagsagat4020 6 ай бұрын
Very clever design, can I assume that one reason that it’s preferable to trigger clk’s rising edge is power consumption because instead of shifting a ‘1’ and the remaining registers are stored with 0’s. For falling edge, we’d be shifting ‘0’ where the remaining registers are stored 1’s(the reset and set bar would need to be rerouted in this scenario). But I’d assume throughout a whole conversion cycle, storing a 1 in many registers for a cycle duration could burn more power than to perhaps shifting 1’s especially for a higher resolution ADC?
@이승현-p8y
@이승현-p8y 8 ай бұрын
beautifull.
@Killergamerz223
@Killergamerz223 9 ай бұрын
🎉
@TNAVYA2395BatchPESUniversity
@TNAVYA2395BatchPESUniversity 9 ай бұрын
What about the remaining sets and resets? what should they be connected to during simulation?
@shekarmsc
@shekarmsc 9 ай бұрын
Please specify what board the TCRT Sensor is connected
@charliee849
@charliee849 10 ай бұрын
gran video, sigue así, nuevo suscriptor
@TechBuild
@TechBuild 10 ай бұрын
Quite insightful.
@bradley8232
@bradley8232 11 ай бұрын
💘 *Promo sm*
@Jesus350X
@Jesus350X 11 ай бұрын
hi whichs book name?
@XindyLi
@XindyLi Жыл бұрын
Good 芭比
@XindyLi
@XindyLi Жыл бұрын
🎉🎉🎉🎉🎉🎉🎉
@koenfrijlink7101
@koenfrijlink7101 Жыл бұрын
Exactly what I want to test but can't see clear the pins.
@abdellahiaioun8430
@abdellahiaioun8430 Жыл бұрын
Thanks man
@volkerraum3494
@volkerraum3494 Жыл бұрын
A Little advice... you should give your posts names reflecting what the lecture will be about. I would never watch posts which I cannot see what they are about.
@andresvenzor
@andresvenzor Жыл бұрын
Cual seria la corriente maxima que maneja el fototransistor?
@LIl-bl9ut
@LIl-bl9ut Жыл бұрын
I click Headache I'm dead
@rezapapi6544
@rezapapi6544 Жыл бұрын
thank you for your amazing videos!
@王禾-d9o
@王禾-d9o Жыл бұрын
Excellent video! Excellent work!
@afaruk18
@afaruk18 Жыл бұрын
can you share the source code for this project
@priyansh_gupta163
@priyansh_gupta163 Жыл бұрын
where are the set_bar of the above d-flipflop and reset_bar of the first d-flipflop and the clock of the last lower d- flipflop connected please tell me as soon as possible I really need help
@harshapeteti4074
@harshapeteti4074 Жыл бұрын
Where is nor gate symbol
@syedanas7398
@syedanas7398 Жыл бұрын
If A2 is set to a 1 by the comparator and say A3 is a 0 from the first clk cycle. Wouldn't A2 then trigger the first register's clk and cause the comparator output (1 in this case) to be latched onto A3, thereby corrupting the data? Or am I missing something here.
@_mixsingh_
@_mixsingh_ 8 ай бұрын
Same doubt, had ur doubt cleared now btw?
@jomelsagsagat4020
@jomelsagsagat4020 6 ай бұрын
Not sure if I understood what was asked. A2 is set to a 1 by the binary shift registers at the top and for A2 to be set to a 1 by the comparator. A1 flip flop would have to trigger clk rising edge on A2 with a comparator output = 1. I believe the confusion is that, the proceeding register(d flip flop) updates the preceding register which is why there’s an extra register to the right to update the last bit A0. So yes, A3 stored ‘0’ at first and was updated to ‘1” accordingly by A2 since A2=1(clk A3 is true) and Comp=1(is true). Next, A2 will get updated accordingly by A1…… the last register A0 will get updated from the addition of “dummy” register. Kind of reminds me of an iteration of the Fibonacci sequence haha By this SAR circuit configuration, it starts at the MSB and trickles down to LSB traditionally. It could probably start at the LSB and move up to the MSB if things were rerouted differently and the dummy register is placed adjacent to MSB register idk.
@ChandrashekarCN
@ChandrashekarCN Жыл бұрын
💖💖💖💖
@vanyalushbaugh6540
@vanyalushbaugh6540 2 жыл бұрын
I'm going to check out your channel now! New fan :)!!! Do what the pros do = promo sm!!!
@therealmum3wisemen
@therealmum3wisemen 2 жыл бұрын
Nice one. I just stubble on this now. After stuffing the internet for days. Please can you help with the code?
@responsiblestudent7938
@responsiblestudent7938 2 жыл бұрын
Sir book name please!!
@selenium.34
@selenium.34 2 жыл бұрын
Hi, can you share the code
@adrianobuhov52
@adrianobuhov52 2 жыл бұрын
Thank you very much, keep up the good work!
@darlene3196
@darlene3196 2 жыл бұрын
Thank you so much. Big help!
@lonelymechanic3688
@lonelymechanic3688 2 жыл бұрын
this helped a lot with my ADC project. thanks.
@gmmukkaramahmed1024
@gmmukkaramahmed1024 2 жыл бұрын
could you please tell how to calculate area using ruler of a layout daigram in mircrowind software
@denebvegaaltair1146
@denebvegaaltair1146 2 жыл бұрын
Omg I get it now. Thank you so much!
@danfarthing4332
@danfarthing4332 2 жыл бұрын
Thank you for your very clear explanations!
@withart6299
@withart6299 3 жыл бұрын
Sir, can you share the wiring or schema please?
@dynastysong
@dynastysong 3 жыл бұрын
Love it. Thank you
@shubhamnayak9369
@shubhamnayak9369 3 жыл бұрын
at 20:23 can i connect VGS between gate and ground and give VGS=-ve?. because i tried doing it and results are not correct.
@josephhuang6585
@josephhuang6585 3 жыл бұрын
Hi sir, If I use current probe to detect the Drain current(Id) whose value is positive in Id-VGS curve. If I use current probe to detect the Source current(Is) whose value is negative in Is-VGS curve. But the current has only one direction from Drain to Source, why one is positive and one is negative ??? thanks a lot.
@josephhuang6585
@josephhuang6585 3 жыл бұрын
Hi sir, in video 20:23, for PMOS why can't I use negative voltage(VGS) .dc VGS 0 -5 0.1to simulate, but must use positive voltage (VSG) ? thanks a lot.
@yiyanli6937
@yiyanli6937 3 жыл бұрын
I think it would work. Did you change the name of the voltage source to VGS? 'VGS' or 'VSG' is just a label but not a polarity.
@yiyanli6937
@yiyanli6937 3 жыл бұрын
@@josephhuang6585 Send your schematic to [email protected] and I'll take a look at it tomorrow.
@josephhuang6585
@josephhuang6585 3 жыл бұрын
thanks for your reminder. If want to use VGS,the voltage source's polarity must be inversed to -+ and type initial value VGS=-5,then the simulation's result will be correct.
@shubhamnayak9369
@shubhamnayak9369 3 жыл бұрын
@@josephhuang6585 mine didnt worked
@chawalitudomsak2072
@chawalitudomsak2072 3 жыл бұрын
Hi sir, can you show me simulation to determine the value of kp or uncox by using LTSPICE? Thank you.
@yiyanli6937
@yiyanli6937 3 жыл бұрын
Sorry for the late response. Please refer to Dr. Baker's CMOS textbook to find the values of kp and cox for the model used in the simulation. www.amazon.com/Circuit-Design-Simulation-Microelectronic-Systems/dp/0470881321/ref=sr_1_2?dchild=1&keywords=cmos+simulation+baker&qid=1616696008&sr=8-2