Perfect this is working and easy.🙏🙏

Bhai maine liya h lekin mobile ke battery connector pe 4.29 hi aa raha ..jab ki 5v ana chahiye

Apple fon ?

bro how to do this plz help me

how to fix limit 12 month can't join

Iska accuracy aacha ha?

worst explanation

Your contact number bro??

How to chate link

🙏🙏🙏🙏

How much cost to build this floating waste collector

Thanks bro 🙏🙏🙏❤

👏👏

भाई मैने बि ऑर्डर किया ता लेकिन उसमे मल्टीमीटर का कवर केस नहीं आया कन्यो? अब तुमरा वीडियो देकर पता चला। अब डेढ़ महीना होगया मैने अमेजन से खरीदा ता।🤔

Even though I didn’t understand the language, I could understand from the video. Thank you so much. It worked!

Quick question, so you're using an external DAC for the FPGA? I was hoping to find an FPGA with DAC capabilities.

Isme capaciter chek nahi ho sakta

TQ BHAI

Current measuring How

Ampere check kr skty hain Ismy???

Bahut sundar 👍👍

👍👍👍

Rhik hai

Is TH-M100 good?

Kaisa h bhai iska response batana please

broo what indicate l and h in nvc mode?

Good

🐱😸😺😸🐱

How to check amps not show in vedio

Brother please can you give me the cadence software file

Bhai, sdc file same hogi kisi v design ke liye? Agar main alu design karunga to v same hogi? Ya fr RAM?

How to measure AC current?

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib 2. read hdl counter.v 3. elaborate 4. read_sdc constraints_top.sdc //Reading Top Level SDC 5. set_db syn_generic_effort medium //Effort level to medium for generic, mapping and optimization 6. set_db syn_map_effort medium 7. set_db syn_opt_effort medium 8. syn_generic 9. syn_map 10. syn_opt //Performing Synthesis Mapping and Optimisation 11. report_timing > counter_timing.rep //Generates Timing report for worst datapath and dumps into file 12. report_area > counter_area.rep //Generates Synthesis Area report and dumps into a file 13. report_power > counter_power.rep //Generates Power Report [Pre-Layout] 14. write_hdl > counter_netlist.v //Creates readable Netlist File 15. write_sdc > counter_sdc.sdc //Creates Block Level SDC

module alu_32bit_case(y,a,b,f); input [31:0]a; input [31:0]b; input [2:0]f; output reg [31:0]y; always@(*) begin case(f) 3'b000:y=a&b; //AND Operation 3'b001:y=a|b; //OR Operation 3'b010:y=~(a&b); //NAND Operation 3'b011:y=~(a|b); //NOR Operation 3'b010:y=a+b; //Addition 3'b011:y=a-b; //Subtraction 3'b100:y=a*b; //Multiply default:y=32'bx; endcase end endmodule Alucase_test.v module alu_32bit_tb_case; reg [31:0]a; reg [31:0]b; reg [2:0]f; wire [31:0]y; alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f)); initial begin a=32'h00000000; b=32'hFFFFFFFF; #10 f=3'b000; #10 f=3'b001; #10 f=3'b010; #10 f=3'b100; end initial#50 $finish; endmodule create_clock -name clk -period 2 -waveform {0 1} [get_port "clk"] set_clock_transition -rise 0.01 [get_clock "clk"] set_clock_transition -fall 0.01 [get_clock "clk"] set_clock_uncertainty 0.01 [get_ports "clk"] set_input_delay -max 0 -clock clk [all_inputs] set_output_delay -max 0 -clock clk [all_outputs] set_load 0.15 [all_outputs]

module jk_latch ( input en, input j, input k, output reg q, output q_bar ); always @(en, j, k) begin if (en) begin case ({j, k}) 2'b00: q <= q; 2'b01: q <= 1'b0; 2'b10: q <= 1'b1; 2'b11: q <= ~q; endcase end end assign q_bar = ~q; endmodule Jkl_test.v module jk_latch_tb; reg en, j, k; wire q, q_bar; jk_latch dut ( .en(en), .j(j), .k(k), .q(q), .q_bar(q_bar) ); initial begin en= 1; j = 0; k = 0; // Test Case 1: Enable and input 'j' and 'k' transitions #5 j = 1; k = 0; #5 j = 0; k = 1; #5 j = 1; k = 1; #5 j = 0; k = 0; // Test Case 2: Disable (asserted enable) #10 en = 0; #5 j = 1; k = 0; #5 j = 0; k = 1; $finish; end endmodule Jkl.sdc create_clock -name en -period 2 -waveform {0 1} [get_port "en"] set_clock_transition -rise 0.01 [get_clock "en"] set_clock_transition -fall 0.01 [get_clock "en"] set_clock_uncertainity 0.01 [get_ports "en"] set_input_delay -max 1.0 -clock en [get_ports "j"] set_input_delay -max 1.0 -clock en [get_ports "k"] set_output_delay -max 1.0 -clock en [get_ports "q"] set_output_delay -max 1.0 -clock en [get_ports "q_bar"] set_load 0.15 [all_outputs]

module jkff(J, K, clk, Q,Qm); input J, K, clk; output reg Q,Qm; always @(posedge clk) begin if(J == 1 && K == 0) Qm = 1; else if(J == 0 && K == 1) Qm = 0; else if(J == 1 && K == 1) Qm = ~Qm; end endmodule Jkff_test.v module jkff_test; reg J,K,clk; wire Q, Qm; jkff uut(.J(J), .K(K), .clk(clk), .Q(Q), .Qm(Qm)); initial begin clk=0; J=0; K=0; #20; J=0; K=1; #20; J=1; K=0; #20; J=1; K=1; #20; $finish; end always #5 clk=~clk; endmodule Jkff.sdc create_clock -name clk -period 2 -waveform {0 1} [get_port "clk"] set_clock_transition -rise 0.01 [get_clock "clk"] set_clock_transition -fall 0.01 [get_clock "clk"] set_clock_uncertainity 0.01 [get_ports "clk"] set_input_delay -max 1.0 -clock clk [get_ports "J"] set_input_delay -max 1.0 -clock clk [get_ports "K"] set_output_delay -max 1.0 -clock clk [get_ports "Q"] set_output_delay -max 1.0 -clock clk [get_ports "Qm"] set_load 0.15 [all_outputs]

module sr_latch ( input s, input r, output reg q, output q_bar ); always @(s, r) begin if (s && !r) q <= 1'b1; else if (!s && r) q <= 1'b0; else if (s && r) q <= q; end assign q_bar = ~q; endmodule Srl_test.v module sr_latch_tb; reg s, r; wire q, q_bar; sr_latch dut ( .s(s), .r(r), .q(q), .q_bar(q_bar) ); initial begin s = 0; r = 0; // Test Case 1: Set (S = 1, R = 0) #5 s = 1; r = 0; Srl_test.v module sr_latch_tb; reg s, r; wire q, q_bar; sr_latch dut ( .s(s), .r(r), .q(q), .q_bar(q_bar) ); initial begin s = 0; r = 0; // Test Case 1: Set (S = 1, R = 0) #5 s = 1; r = 0; #5 s = 0; r = 0; // Test Case 2: Reset (S = 0, R = 1) #5 s = 0; r = 1; #5 s = 0; r = 0; // Test Case 3: Invalid state (S = 1, R = 1) #5 s = 1; r = 1; #5 s = 0; r = 0; $finish; end endmodule Srl.sdc create_clock -name en -period 2 -waveform {0 1} [get_port "en"] set_clock_transition -rise 0.01 [get_clock "en"] set_clock_transition -fall 0.01 [get_clock "en"] set_clock_uncertainity 0.01 [get_ports "en"] set_input_delay -max 1.0 -clock en [get_ports "s"] set_input_delay -max 1.0 -clock en [get_ports "r"] set_output_delay -max 1.0 -clock en [get_ports "q"] set_output_delay -max 1.0 -clock en [get_ports "q_bar"] set_load 0.15 [all_outputs]

module sr_ff(SR,clk,Q,Qbar); input [1:0] SR; input clk; output reg Q,Qbar; always@(posedge clk) begin case(SR) 2'b00: Q = Q; 2'b01: Q = 0; 2'b10: Q = 1; 2'b11: Q = 1'bx; endcase Qbar = ~Q; end endmodule Srff_test.v module sr_ff_test(); reg [1:0]SR; reg clk; wire Q,Qbar; sr_ff uut (.SR(SR), .clk(clk), .Q(Q), .Qbar(Qbar)); always #5 clk =~clk; initial begin clk =0; SR=0; #10 SR = 2'b00; #10 SR = 2'b01; #10 SR = 2'b10; #10 SR = 2'b11; #40 $finish; end endmodule Srff.sdc create_clock -name clk -period 2 -waveform {0 1} [get_port "clk"] set_clock_transition -rise 0.01 [get_clock "clk"] set_clock_transition -fall 0.01 [get_clock "clk"] set_clock_uncertainity 0.01 [get_ports "clk"] set_input_delay -max 1.0 -clock clk [get_ports "S"] set_input_delay -max 1.0 -clock clk [get_ports "R"] set_output_delay -max 1.0 -clock clk [get_ports "Q"] set_output_delay -max 1.0 -clock clk [get_ports "Qbar"] set_load 0.15 [all_outputs]

module DFF( Q,Qbar,D,clk,reset); output reg Q; output Qbar; input D,clk,reset; always @(posedge clk) begin if (reset == 1'b1) Q <= 1'b0; else Q <= D; end assign Qbar = ~Q; endmodule module DFF_test(); reg D; reg clk; reg reset; wire Q; DFF uut (.Q(Q), .Qbar(Qbar), .D(D), .clk(clk), .reset(reset)); initial begin clk = 1'b0; forever #20 clk = ~clk ; end initial begin reset = 1'b1; #40; reset = 1'b0; #40; D = 1'b0; #40; D = 1'b1; #40; $finish ; end endmodule create_clock -name clk -period 2 -waveform {0 1} [get_port "clk"] set_clock_transition -rise 0.01 [get_clock "clk"] set_clock_transition -fall 0.01 [get_clock "clk"] set_clock_uncertainity 0.01 [get_ports "clk"] set_input_delay -max 1.0 -clock clk [get_ports "Reset"] set_input_delay -max 1.0 -clock clk [get_ports "D"] set_output_delay -max 1.0 -clock clk [get_ports "Q"] set_output_delay -max 1.0 -clock clk [get_ports "Qbar"] set_load 0.15 [all_outputs]

`timescale 1ns/1ps module counter(clk,rst,m,count); input clk,rst,m; output reg [3:0]count; always@(posedge clk or negedge rst) begin if(!rst) count=0; else if(m) count=count+1; else count=count-1; end endmodule `timescale 1ns/1ps module counter_test; reg clk, rst,m; wire [3:0] count; initial begin clk=0; rst=0;#25; rst=1; end initial begin m=1; #60 m=0; rst=0;#25; rst=1; #50 m=0; end counter counter1(clk,rst,m, count); always #5 clk=~clk; initial #1400 $finish; create_clock -name clk -period 2 -waveform {0 1} [get_port "clk"] set_clock_transition -rise 0.01 [get_clock "clk"] set_clock_transition -fall 0.01 [get_clock "clk"] set_clock_uncertainity 0.01 [get_ports "clk"] set_input_delay -max 0.8 [get_ports "rst"] -clock [get_clocks "clk"] set_output_delay -max 0.8 [get_ports "count"] -clock [get_clocks "clk"] set_input_transition 0.12 [all_inputs] set_load 0.15 [all_outputs]

Please make 6T and 10T sram based video in cadence. No proper video available. Please

❤❤❤❤❤

Good work 🎉🎉

🔥 🔥

This product is available in pakistan

I enjoyed this presentation. If accessible, and primarily for fun, using Ansys HFSS to simulate the portable microwave magnetron 2.45Ghz radiation output via waveguides into the cooking chamber is a rewarding & multifaceted challenge to undertake.

👏👏👍👍

Can we measure capacitance??

मैं बहुत दुखी हूं इसलिए कि इनमें AC ampere नहीं है 😢😢😢😢😢💔💔💔