I tried to adapt the design to an fsk where the FCW changes based on an input bit but I get a distorted sine wave for very high frequencies in the range of MHZ and for low frequencies around 40KHz I get a nice FSK output. Do you have any idea why it does this? I would like to design an fsk with center frequency around 100MHz or more

I want to use this to design an FSK Modulation scheme, can I just ignore the cosine and use just the sine wave output for my system?

You saved some lives with this video

Noce, guys i see your future brighter. This is going to be one of the best channel for FPGAs. One advice, if possible present some brief theory as well. Thanks

Thank you for sharing this video. Would you be able to create another video explaining the DDS compiler IP?

Great Video! I have a question: How can we define the RX and TX buffer addresses?

This video demonstrates the use of two ARM cores, but the methodology can be extended to add more domains to your platform project, allowing you to run multiple ARM cores with different operating systems simultaneously!

From the ARM core's perspective, the FPGA and peripherals are memory-mapped entities. ✅Access to everything is done using their addresses and offsets. ✅The simplest way to access any memory address is by using a volatile pointer, along with Xil_Out and Xil_In functions.

I bought my board second-hand from eBay at a fair price! 💸 However, some of you might find the ZCU104 a bit on the expensive side. 💰💰💰

I always love to include a blinking LED 💡in my designs! it makes it much easier to tell that the FPGA is alive 🫀 and running smoothly.

This is my experience♠: whenever you need a driver, especially for standalone or FreeRTOS, the first place to search 🔍is the Xilinx GitHub repository. ✅ You'll often find the appropriate examples there!

The first and simplest step when using the AXI DMA is to run it in loopback mode🔄. However, I’d like to engage your thinking 🧠with a simple question: How can we send data directly from the PL to DDR?😎 If I have a basic counter in the PL, how can I transmit the counter output to DDR?🥸

📢 In the previous videos, I demonstrated how to generate Sine and Cosine waves using a LUT (BRAM). In this video, I will cover the CORDIC algorithm for wave generation. The choice between using a LUT or CORDIC ❓ depends on your design requirements, such as: ✔Arbitrary vs. Fixed Wave Generation: If your design allows dynamic changes to the BRAM content, you can generate a variety of waves, not just Sine and Cosine. ✔Required Output Resolution: Consider the resolution needed for your application. ✔Available FPGA Resources: Decide whether to prioritize BRAM or DSP resources based on availability and efficiency needs.

Hello, Can you please provide information on how to mount the M.2 SSD on the ZCU104 board. I have bought an M.2 SSD and connected it to the ZCU104 board, but when I type the lsblk command in the PYNQ terminal the SSD is not showing up. is there any steps to enable the SSD is so can you share that?

thanks for this great clip. my question is when I have 2 application code on each core for dualcore zynq. How I can do this procedure?

7:48 FMC, can you run the loopback card in future videos ? Thanks

Thanks! I didn't know we can run a simulation in Vivado that much easy! Is it possible to create a training for real Vivado implementation and synthesis please?

It's very clear! Love it!👍

😀 Thank you for the explanation. I/O pin planning part is quite interesting.

Greate Video! Continue!

Great!