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@TheBestRussianPub
@TheBestRussianPub 3 ай бұрын
In addition to the tutorial, I also got to ASMR.😁
@khaled_ismail
@khaled_ismail 6 ай бұрын
Many thanks for the detailed walkthrough. Very helpful.
@nach1113
@nach1113 7 ай бұрын
Awesome class! This level of detail is hard to come by. Thanks a lot!
@RandomHubbb
@RandomHubbb 7 ай бұрын
Best explanation that has ever been done! Thank you so much for this!
@elruby
@elruby 8 ай бұрын
can you provide a tutorial if i want to use riscv-dv on my riscv rtl cuz the documentation of riscv-dv is very poor
@SivaCharan-o2j
@SivaCharan-o2j 9 ай бұрын
i want license link where did i find it
@petarmilanov5443
@petarmilanov5443 11 ай бұрын
Thank you for the effort to create one hour video. I listened 2-3 minutes and closed it. The quality of the sound is one of the worst I ever heard. ALDEC, do you care :) ?
@akshatparwani4961
@akshatparwani4961 Жыл бұрын
is it real or ai voice
@Omkar.S-n1g
@Omkar.S-n1g Жыл бұрын
How can a Windows user use COCOTB with Riviera-pro? I am using COCOTB in MING(msys2 environment). Tried installing ACTIVE-HDL but it didn't work.
@henddawood1692
@henddawood1692 Жыл бұрын
Check Active HDL and verilog tutorial in Arabic here kzbin.info/aero/PLkRMjfNn5j2oIrn8Sthn_1JGKQTWJdoVN
@mmzf2357
@mmzf2357 Жыл бұрын
Best tutorial 👍🏻
@prajishp.j1180
@prajishp.j1180 Жыл бұрын
Everywhere it is mentioned that UVM sequence is a collection of sequence items.So suppose I have 2 sequence items ,one for write , one for read..does this mean a single sequence can have both the sequence items..in all examples there s one sequence for one sequence items..then how is sequence a collection of sequence items??
@amey97
@amey97 Жыл бұрын
Thank You!
@rossh9892
@rossh9892 Жыл бұрын
I loved this especially the ending. It would be easy for you to get your subs up with 'Promo SM'!!
@historyproof6722
@historyproof6722 Жыл бұрын
Hello, can you tell me in the active hdl program you can create libraries like in Viriera Pro for System Vue?
@rickzhi5498
@rickzhi5498 2 жыл бұрын
Thank you
@muraliguptapenugonda9257
@muraliguptapenugonda9257 2 жыл бұрын
Very helpful , could you please tell me in which tool you are doing it?
@lokesh.3814
@lokesh.3814 2 жыл бұрын
Modelsim
@ibrahimmetebingol7526
@ibrahimmetebingol7526 2 жыл бұрын
When ı write command "apio verify", ı get this error: module 'click' has no attribute 'get_terminal_size' Can u help me? I dont understand why
@PradeepSingh-kp6tu
@PradeepSingh-kp6tu 2 жыл бұрын
nice :))
@lk67sk64
@lk67sk64 2 жыл бұрын
Watching such technical videos is an Absolute waste of time!
@BrianThomas
@BrianThomas 2 жыл бұрын
@aldecinc So, here's the thing. Great video by the way. I've been looking all over and yours ranks up there in how you explain what Verilog even is . I love electronics. What's your advice for someone like me who's struggling to understand what you're taking about in this video. I don't know C+ but I do understand Python.
@bigoboss-bn5mc
@bigoboss-bn5mc Жыл бұрын
he's using verilog/vhdl not C++
@rushikeshkarande3207
@rushikeshkarande3207 2 жыл бұрын
Can you please provide those steps, I am getting some error while integrating. I have run one bease test but not able to compare both rtl as well as spike
@yulonglan132
@yulonglan132 Жыл бұрын
do you know how to use verilator to compile and instantiate an ibex core?
@emilyfeuerstein4349
@emilyfeuerstein4349 2 жыл бұрын
I bought this product through a friend's recommendation and we just will not go to any other board. PLEASE everybody do yourself a favor, and purchase this immediately. Thank you! :)
@boddisk
@boddisk 2 жыл бұрын
Nothing happens when I click the "Highlight Coverage Lines" Icon
@satvlsi2171
@satvlsi2171 2 жыл бұрын
For Latest VLSI Job Update's and HDL Learning Please follow below :weekendvlsi.blogspot.com/2021/11/weekend-vlsi-home.html careersinvlsi.blogspot.com/2021/11/main-menu.html
@angadpattnaik3508
@angadpattnaik3508 2 жыл бұрын
Beautiful Explanation
@yousifmousa2061
@yousifmousa2061 2 жыл бұрын
What simulator did you use? Is it free?
@jram8961
@jram8961 2 жыл бұрын
Rivera Pro. I guess it is not free
@rabiahir7576
@rabiahir7576 3 жыл бұрын
Hi can you guide me how to open asdb file..
@jacobchen9858
@jacobchen9858 3 жыл бұрын
What I was looking for!
@ingenieurengeener5298
@ingenieurengeener5298 3 жыл бұрын
Name of program using please?
@cavver3523
@cavver3523 3 жыл бұрын
Quartus Prime
@disenoelectronico7022
@disenoelectronico7022 3 жыл бұрын
EDA playground, online mode: kzbin.info/www/bejne/eIfOaGefZ5xje6c
@miracle7lee
@miracle7lee 2 жыл бұрын
Riviera pro
@sumanthnimmakayala2271
@sumanthnimmakayala2271 3 жыл бұрын
Sir, your video was very good, So i need your help for my HDL code to prepare testbench code for that. so can you able to give your email id so that i will be in contact with you for my help or else my mail id [email protected]
@vasilisnikitaras
@vasilisnikitaras 3 жыл бұрын
Amazing!
@ganeshbhogaraju4558
@ganeshbhogaraju4558 4 жыл бұрын
Aldec has very rich source of valuable documentation.
@guitarmenace1981
@guitarmenace1981 4 жыл бұрын
6 people don't understand virtual interfaces.
@jackjones5187
@jackjones5187 4 жыл бұрын
Great information on DO-254 and avionics testing - thank you for posting. Also I found this additional free DO-254 paper (which is avionics hardware) on the web also - ample additional information on DO-254 and they have other free info and technical data on DO-178C, ARP4754A, DO-278A, etc., here: afuzion.com/do-254-introduction/ - Enjoy, Jack.
@babytwum
@babytwum 4 жыл бұрын
This is really a good video for DO 254. I found another one worth to watch here kzbin.info/www/bejne/gafTnGh3lKx1fMU
@uday5786
@uday5786 4 жыл бұрын
can we send multiple transactions at a time to driver (in one get_next_item ....item_done loop)
@bakeronews1
@bakeronews1 4 жыл бұрын
How you got to the test bench???????????? Stop skipping steps!!!!!!
@nshuang1009
@nshuang1009 4 жыл бұрын
This is a very good video for a hardware engineer. Do you provide any paid UVM training course? If yes, where can I find the course information?
@sivakumar-lb5pk
@sivakumar-lb5pk 4 жыл бұрын
Which software tool you used here ?
@atif_hamza
@atif_hamza 4 жыл бұрын
its Xilinx ISE , i think
@dn2358
@dn2358 3 жыл бұрын
@@atif_hamza no I guess it's modelsim
@LongHoang-xl7vj
@LongHoang-xl7vj 3 жыл бұрын
at the end of the video he showed the software which he used in the video. its name is riviera pro simulator
@trunganhnguyenthanh2768
@trunganhnguyenthanh2768 4 жыл бұрын
Really interesting, but what's the point for using python to verify a HDL code, I mean what's its benefit ? Is there something which python can do but normal HDL languages ( Verilog, VHDL) can't in a testbench ?
@JNeverMindMe
@JNeverMindMe 3 жыл бұрын
Yes: calling other software like C executables, or calling other TCL scripts, which allows for easier integration in a software environment. Why would you want to do that? Well, maybe you can integrate your HDL TB, as done in CocoTB in an environment where you want to plot the outputs of your RTL block, or open files in more user friendly manner to drop log messages, read them to provide stimulus for a RTL designed block, or comparing its outputs with golden cases that are stored in files. VHDL does file management as reading and writing on them, which is great. But Python has a more user friendly approach for the same task. All in all, if you want a fully fledged verification environment, you can do the following: * Build a RTL (VHDL for example) only verification environment; procedures, functions, files, etc... * Build a RTL + TCL verification environment; rtl procedures, functions, files or tcl functions, files, etc... * Build a RTL + Python verification environment; rtl procedures, functions, files, or python classes with functions, files, etc... As I've said before. If you design a Digital Signal Processing block, that accepts and generates data in bulk, verying its output is easier in Python, if numpy gives you enough functions to create signals such as a sine function, or plotting the immediate outputs of the RTL block. And if you don't, Python still offers a lot of solutions for immediate stimulus generation or output verification of an RTL block, that otherwise, needs to be generated via TCL, or without TCL, maybe given via stimulus and output files, which has a bit more steps to it.
@redhouanedjellali920
@redhouanedjellali920 4 жыл бұрын
please how to create testbench file c+
@ya3525
@ya3525 4 жыл бұрын
Can you please give an idea of the price?
@absolute___zero
@absolute___zero 4 жыл бұрын
I am looking for an FPGA board to build a feed-forward neural net, could you tell how many LUTs/Logic Cells are required to build a network with 10 inputs, 10 neurons on the hidden layer, and 10 neurons on the output layer? Just an approximate. I kind of, need to estimate the requierd FPGA size for my app.
@aldecinc
@aldecinc 4 жыл бұрын
Hi, please create a an account on our website and submit this as a support case so one of our engineers may contact you. Customer Portal link: bit.ly/333gXzL
@alihoseinporyamoazam4118
@alihoseinporyamoazam4118 4 жыл бұрын
please insert link of file
@beaug83
@beaug83 5 жыл бұрын
From this video I understand that I will be watching a "please wait" spinner.
@antona7581
@antona7581 5 жыл бұрын
Where to buy?
@azaira010
@azaira010 5 жыл бұрын
Make a videos for windows!!!
@saikiranvilla
@saikiranvilla 9 ай бұрын
yes
@manojrr87
@manojrr87 5 жыл бұрын
Hi, thanks for this tutorial. But, where can we find the OOP and TLM webinar?. It is not there in your channel
@aldecinc
@aldecinc 5 жыл бұрын
Hi, we have new webinars coming out all the time and it may be located on our website. If you still cannot locate it please contacts us directly.