mashallah

elmores delay ka ye tareeqa theek nai hai

Sir you taught so well clearing the concept of delay Thank you sir 🙏

why did you use the xor in the end and delete the previous layout.

Derive the equation of propagation Delay using RC Delay Model for a1 st order system answer

One of the worst videos on this subject matter I have seen!

Do you have social media accounts?

Awesome

Hey! Can you please make a video on the topic below:{ Design of 8-to-1 Multiplexer (MUX) using both cases of (1) only transmission gates (TG) and (2) conventional CMOS gates.} This video helped me understand the concepts for one of my assignments. Also, if there is any contact information please do let me know! Thank you!

Sir i had soo many questions in this topic. And after hours of watching other videos, i came across yours. Thankyou for such wonderful presentation. I cleared most of my doubts!!

When we are trying to calculate the value of k for a our circuit so that it becomes equivalent to the resistance of a unit invert. Do we take the longest path in pull up and pull down as well ?

Great lesson. Was wondering how routing works in FPGAs and got detailed yet simple explanation. Subscribed)

How parasitic delay is=1 In first question ❓

Good Lecture. It gave great insight into the Architecture of LUTs. Jazakallah

Sir how we will find effective resistance in logical effort?

Why is nmos is 3 why not 4 or 2

Doesn't the LUT contain 8x2 bits = 16 bits of memory, if you use the 3 inputs as address instead of 2 bits? Wouldn't the LUT requirement for 1 MB memory go down from 4M to 512K LUTs?

Great, thanks a lot.

Thank you sir.. this helped me a lot, couldn't find this kind of info on LUT anywhere else.

this video is precious

Which book you used.

How to measure throughput of any circuit in fpga??

I need Verilog Code for LUT

Can u help me with a problem

Which university you teach ? Thanks today our prof conducted this lecture

Thanks for the lecture

One question. why aren't we considering the source and drain component capacitances for series nmos junction nodes? for eg, why is it 3C instead of 3C (drain of below nmos) + 3C (source of above nmos) = 6C. I got confused about this as for a cmos inverter, the 3C is calculated by adding 2C (pmos drain cap) and 1C (nmos drain cap). Please correct me if I'm being wrong. Thanks

how to download lecture slides

Hi, Thanks a lot for such valuable information. I have got a couple of questions regarding LUT's 1) how can we implement a 4 input LUT using two input LUT? 2) can we use output from LUT's to map the sram bits in another LUT?

If I draw 10 such nand gates will the simulation be same for 10 input nand gate?

It's really helpful! Thank you :D

thanks, a lot for this great explaining, i am looking forward for more great videos