verilog revision class -2 by DEV
1:32:15
verilog revision class -2 by DEV
21 сағат бұрын
verilog revision class -1 by dev
1:44:44
verilog revision class -1 by dev
21 сағат бұрын
FSM implementation in FPGA by gopi@DEV's VLSI training institute
3:27
FSM implementation in FPGA by gopi@DEV's VLSI training institute
Ай бұрын
ethernet XGMII lecture
6:07
ethernet XGMII lecture
Ай бұрын
comb,latch, flip flop, unwanted latch,comb followed by flip flop in behavioural style
51:10
comb,latch, flip flop, unwanted latch,comb followed by flip flop in behavioural style
Ай бұрын
verilog vs SV
40:05
verilog vs SV
Ай бұрын
preset,clear,synchronous vs asynchronous inputs, implementation of latches and flip flops with MUX
21:41
preset,clear,synchronous vs asynchronous inputs, implementation of latches and flip flops with MUX
Ай бұрын
JK,T gated latches and flip flops, master slave JK flip flop, conversion of flip flops
1:02:12
JK,T gated latches and flip flops, master slave JK flip flop, conversion of flip flops
Ай бұрын
D,SR gated latches(+ve,-ve levels) and flip flops(+ve,-ve edges),state diagram of flip flops
1:03:37
D,SR gated latches(+ve,-ve levels) and flip flops(+ve,-ve edges),state diagram of flip flops
Ай бұрын
SR non gated NOR latch working,Active high latch,Sbar Rbar latch,SR NAND gated latch
49:14
SR non gated NOR latch working,Active high latch,Sbar Rbar latch,SR NAND gated latch
2 ай бұрын
sequential circuits introduction,comb vs sequi,non gated SR NAND latch working,latch vs flip flop
1:03:28
sequential circuits introduction,comb vs sequi,non gated SR NAND latch working,latch vs flip flop
2 ай бұрын
DEVs VLSI Training Institute e learning DV course demo lecture
21:27
DEVs VLSI Training Institute e learning DV course demo lecture
2 ай бұрын
UDP in gate-structural modellings,why we don't code sequential circuits in data flow-gate-structural
39:00
UDP in gate-structural modellings,why we don't code sequential circuits in data flow-gate-structural
2 ай бұрын
#inertial delay, signal #strengths,analization of waveform with delays in design code #DEV #DV
46:47
#inertial delay, signal #strengths,analization of waveform with delays in design code #DEV #DV
2 ай бұрын
#rise #fall #turn off #min #typical #max delays #bufif0 #bufif1 #notif0 #notif1 #gate delays #DEV
52:48
#rise #fall #turn off #min #typical #max delays #bufif0 #bufif1 #notif0 #notif1 #gate delays #DEV
2 ай бұрын
#distributive #lumped #path delay(parallel,full) #specify block #specparam,delay back annotation
41:15
#distributive #lumped #path delay(parallel,full) #specify block #specparam,delay back annotation
2 ай бұрын
user defined primitive for combinational and sequential circuits #UDP #DEV #DV #primitive vs module
49:18
user defined primitive for combinational and sequential circuits #UDP #DEV #DV #primitive vs module
2 ай бұрын
user defined primitive for combinational and sequential circuits #UDP #DEV #DV #primitive vs module
1:35:53
user defined primitive for combinational and sequential circuits #UDP #DEV #DV #primitive vs module
2 ай бұрын
#System tasks #$display #$write #$strobe #$monitor #$stop #$finish #DV #VLSI #DEV #verilog
55:41
#System tasks #$display #$write #$strobe #$monitor #$stop #$finish #DV #VLSI #DEV #verilog
2 ай бұрын
#System tasks #$display #$write #$strobe #$monitor #$stop #$finish #DV #VLSI #DEV #verilog
54:00
#System tasks #$display #$write #$strobe #$monitor #$stop #$finish #DV #VLSI #DEV #verilog
2 ай бұрын
#parameterizable designs #generate block #genvar #parameter overriding #defparam #localparam #DEV
1:05:05
#parameterizable designs #generate block #genvar #parameter overriding #defparam #localparam #DEV
2 ай бұрын
#UVM #TB explanation from very basics, execution in #EDA and #questasim, #verification with UVM
1:13:19
#UVM #TB explanation from very basics, execution in #EDA and #questasim, #verification with UVM
2 ай бұрын
#gate level modelling for combinational circuits #DV #VLSI #DEV
34:48
#gate level modelling for combinational circuits #DV #VLSI #DEV
2 ай бұрын
#carry #save,#carry #skip,#carry #select,#BCD,#XS3 adders design and working #DV #VLSI #DEV
45:41
#carry #save,#carry #skip,#carry #select,#BCD,#XS3 adders design and working #DV #VLSI #DEV
2 ай бұрын
ripple carry,carry look ahead,adder subtractor, ripple borrow subtractor, subtraction with adders
1:03:36
ripple carry,carry look ahead,adder subtractor, ripple borrow subtractor, subtraction with adders
2 ай бұрын
#half #full #serial adder design and working #half #full subtractors #half adder in data flow
1:15:09
#half #full #serial adder design and working #half #full subtractors #half adder in data flow
2 ай бұрын
#multiplier #design and verification of comparator #code converter #DV #VLSI #DEV
1:15:42
#multiplier #design and verification of comparator #code converter #DV #VLSI #DEV
2 ай бұрын
DV new course demo by DEV
8:44
DV new course demo by DEV
2 ай бұрын
design and verification of #encoder #decoder #DEV #DV #VLSI
1:01:07
design and verification of #encoder #decoder #DEV #DV #VLSI
2 ай бұрын
Пікірлер