Negative Setup time and Hold time || STA 10 @knowledgeunlimited
9:02
Negative Setup time and Hold time || STA 10 @knowledgeunlimited
9 ай бұрын
Setup time and Hold time Question series || STA 9 || DigiQ @knowledgeunlimited
6:27
Setup time and Hold time Question series || STA 9 || DigiQ @knowledgeunlimited
Жыл бұрын
Setup time & Hold time Interview Questions || STA 8 || DigiQ @knowledgeunlimited
11:00
Setup time & Hold time Interview Questions || STA 8 || DigiQ @knowledgeunlimited
Жыл бұрын
Setup time Interview questions || STA 7 || DigiQ @knowledgeunlimited
9:04
Setup time Interview questions || STA 7 || DigiQ @knowledgeunlimited
Жыл бұрын
Skew Timing Analysis || STA Tutorial6 || positive & Negative Skew Analysis @knowledgeunlimited
8:45
Skew Timing Analysis || STA Tutorial6 || positive & Negative Skew Analysis @knowledgeunlimited
Жыл бұрын
Hold Time Analysis || STA Tutorial5 || @knowledgeunlimited #interview
8:03
Hold Time Analysis || STA Tutorial5 || @knowledgeunlimited #interview
Жыл бұрын
Setup time example || STA Tutorial4 || Example Question @knowledgeunlimited #interview
10:46
Setup time example || STA Tutorial4 || Example Question @knowledgeunlimited #interview
Жыл бұрын
Setup Time Analysis continued || STA Tutorial 3 || @knowledgeunlimited #interview
14:33
Setup Time Analysis continued || STA Tutorial 3 || @knowledgeunlimited #interview
Жыл бұрын
Setup Time Analysis continued || STA Tutorial 2 || @knowledgeunlimited
12:56
Setup Time Analysis continued || STA Tutorial 2 || @knowledgeunlimited
Жыл бұрын
Setup time Analysis || STA Tutorial 1 ||@knowledgeunlimited @VLSI
11:11
Setup time Analysis || STA Tutorial 1 ||@knowledgeunlimited @VLSI
Жыл бұрын
NVIDIA Interview Experience || Offline Process || ASIC Engineer || N. Ex. T Program || Vinay Kumar S
35:46
NVIDIA Interview Experience || Offline Process || ASIC Engineer || N. Ex. T Program || Vinay Kumar S
Жыл бұрын
Qualcomm Interview Experience and Questions || Digital Domain
7:47
Qualcomm Interview Experience and Questions || Digital Domain
2 жыл бұрын
Texas Instruments Interview Experience || Digital & Analog || #TIer #Interview @knowledgeunlimited
9:54
Texas Instruments Interview Experience || Digital & Analog || #TIer #Interview @knowledgeunlimited
2 жыл бұрын
FPGA Dumping || Hardware Implementation ||#Spartan 3E| |#xilinx ||# FPGA @knowledgeunlimited
10:29
FPGA Dumping || Hardware Implementation ||#Spartan 3E| |#xilinx ||# FPGA @knowledgeunlimited
2 жыл бұрын
Tutorial 36: Verilog code of Parallel In serial Out Shift Register || #PISO @knowledgeunlimited
4:03
Tutorial 36: Verilog code of Parallel In serial Out Shift Register || #PISO @knowledgeunlimited
3 жыл бұрын
Tutorial 35: Verilog code of serial In serial Out Shift Register || #SISO @knowledge unlimited
3:02
Tutorial 35: Verilog code of serial In serial Out Shift Register || #SISO @knowledge unlimited
3 жыл бұрын
Tutorial 34: Verilog code of parallel In parallel Out Shift Register || #PIPO @knowledgeunlimited
1:59
Tutorial 34: Verilog code of parallel In parallel Out Shift Register || #PIPO @knowledgeunlimited
3 жыл бұрын
Tutorial 33: Verilog code of Serial In parallel Out Shift Register || #SIPO @knowledgeunlimited
3:45
Tutorial 33: Verilog code of Serial In parallel Out Shift Register || #SIPO @knowledgeunlimited
3 жыл бұрын
Tutorial 32: Verilog code of SRFF (UDP) || #udp || #VLSI || #Verilog @knowledgeunlimited
4:15
Tutorial 32: Verilog code of SRFF (UDP) || #udp || #VLSI || #Verilog @knowledgeunlimited
3 жыл бұрын
Tutorial 31: Verilog code of DFF (UDP) || #udp || #VLSI || #Verilog @knowledgeunlimited
4:12
Tutorial 31: Verilog code of DFF (UDP) || #udp || #VLSI || #Verilog @knowledgeunlimited
3 жыл бұрын
Tutorial 30: Verilog code of SR Flip Flop || #VLSI || #Verilog @knowledgeunlimited
3:46
Tutorial 30: Verilog code of SR Flip Flop || #VLSI || #Verilog @knowledgeunlimited
3 жыл бұрын
Tutorial 29: Verilog code of T Flip Flop || #VLSI || #Verilog @knowledgeunlimited
3:54
Tutorial 29: Verilog code of T Flip Flop || #VLSI || #Verilog @knowledgeunlimited
3 жыл бұрын
Tutorial 28: Verilog code of JK Flip Flop || #VLSI || #Verilog @knowledgeunlimited
3:46
Tutorial 28: Verilog code of JK Flip Flop || #VLSI || #Verilog @knowledgeunlimited
3 жыл бұрын
Tutorial 27: Verilog code of D Flip Flop || #VLSI || #Verilog @knowledgeunlimited
6:11
Tutorial 27: Verilog code of D Flip Flop || #VLSI || #Verilog @knowledgeunlimited
3 жыл бұрын
Tutorial 26: Verilog code of Priority Encoder|| #VLSI || #Verilog
3:09
Tutorial 26: Verilog code of Priority Encoder|| #VLSI || #Verilog
3 жыл бұрын
Tutorial 25: Verilog code of 8 to 3 Encoder|| #VLSI || #Verilog
5:51
Tutorial 25: Verilog code of 8 to 3 Encoder|| #VLSI || #Verilog
3 жыл бұрын
Tutorial 24: Verilog code of 1 to 8 de-mux using Instantiation concept || #Verilog || #VLSI
5:17
Tutorial 24: Verilog code of 1 to 8 de-mux using Instantiation concept || #Verilog || #VLSI
3 жыл бұрын
Tutorial 23: Verilog code of 1 to 2 de-mux using if statement || #Verilog || #VLSI
2:46
Tutorial 23: Verilog code of 1 to 2 de-mux using if statement || #Verilog || #VLSI
3 жыл бұрын
Tutorial 22: Verilog code of 1 to 2 de-mux using Case statement || #Verilog || #VLSI
2:29
Tutorial 22: Verilog code of 1 to 2 de-mux using Case statement || #Verilog || #VLSI
3 жыл бұрын
Пікірлер
@saiharshith1002
@saiharshith1002 3 күн бұрын
If anyone looking for solution to the last counter question. It is a simple question. if you assume the counter is [c2,c1,c0] and input is i, the circuit output will be [c2,c1,c0,i]. the process of though is the output looks like 2*c + i. Shift left the counter count by one bit and add i. as i is one bit only the output would be [c2,c1,c0,i]
@MaheshDalle-g5g
@MaheshDalle-g5g 17 күн бұрын
thank you so much
@anudeepb2278
@anudeepb2278 28 күн бұрын
Sir updown counter pls
@vinayagavv10
@vinayagavv10 Ай бұрын
video starts @ 2:18
@kotasiva6144
@kotasiva6144 Ай бұрын
What was the starting mechanical engineering salary as a fresher
@bennguyen1313
@bennguyen1313 Ай бұрын
Would love to know the history behind Enjoy-Digital , Catherine/Whitequark and AmaranthHDL. From what I understand, Travis Goodspeed originally commissioned Enjoy-Digital to make LiteX, which is described in Migen... this later became nMigen, but seems this now has a fork to Amaranth HDL... and there seems to be a dispute in the M-Labs and whitequark (former affiliate of M-Labs?) over the direction/brand of nMigen. Also, any thoughts how it compares to Chisel or Spinal HDL? Any thoughts on PyHDI/Pyverilog/PyVHDL/pyHDI? For example isn't VexRiscv for litex written in SpinalHDL? I'd like to do an SoC based design for a Trenz SMF2000 board.. using either LambdaSoc (Amaranth HDL) or LiteX (m-labs or whitequark's Migen/MiSoc). Ideally, I'd like to leverage off-the-shelf IPs (litescope, , ValentyUSB, minerva or VexRiscV). The goal is a bridge that allows a CPU master to access AHB-Lite and APB3 slaves, all from the Cortex-M3's AHB Fabric-Interface-Controller. (BTW, there's a great blog post on CrowdSupply for Cynthion titled "Moondancer: A Facedancer backend for Cynthion") Also, the debugging tools available for software development have become very sophisticated.. with advanced breakpoint capability, stepping, realt-time variable watching (swv), etc.. with HDLs, it seems the process of debugging hasn't changed and still requires manually writing thousands of test-benches! (Altera's old Max+Plus II Waveform Editor you can could draw your waveforms, then simulate!) Do you know if there's been any development in the area debugging of logic? Everything I've seen still uses test-benches (Icarus Verilog, Verilator/signalflip-js, Aldec Active-HDL, Metrics Cloud Simulator, GHDL for VHDL)!
@DeekshaSehgal-f7b
@DeekshaSehgal-f7b Ай бұрын
sir can you please tell us how much time they have given to us and how many questions are there in the exam ? it will be really helpful.
@senthilmurugankumaravel3902
@senthilmurugankumaravel3902 2 ай бұрын
Wheather training is free of cost
@Sooha_2.0
@Sooha_2.0 2 ай бұрын
Awesomeeeee.. Explanation 😊
@tuhinmondal8750
@tuhinmondal8750 2 ай бұрын
Mai medha servo drive pai as a diploma service engineer select hua but Medha pai increment process pata nahi hai please increment after 1 yr kitna milta hai bata dona plz
@knowledgeunlimited
@knowledgeunlimited 2 ай бұрын
At the time of my placement I feel it’s bi annual increment. I’m not fully aware if any changes happened in that aspect.
@tuhinmondal8750
@tuhinmondal8750 2 ай бұрын
@@knowledgeunlimited can you share your number
@veerayyavastrad
@veerayyavastrad 2 ай бұрын
Hi sir Actually, I'm working on a machine learning research paper. Hardware Acceleration for Machine Learning in Autonomous Vehicles: FPGA and ASIC-based Architectures for Enhanced Performance and Efficiency will be please send me the python and verilog codes. Thank you
@subhasishnayak6365
@subhasishnayak6365 2 ай бұрын
Please share more sta questions and concepts
@gokulmj2004
@gokulmj2004 3 ай бұрын
bro can you explain tessolve semiconductor interview qns
@samarpras
@samarpras 3 ай бұрын
Plz apna number de
@AlphaEngineer-xr7oq
@AlphaEngineer-xr7oq 3 ай бұрын
1:52 important
@SahilKumar-wk2fh
@SahilKumar-wk2fh 3 ай бұрын
AT 5:29 WHAT IS THE NAME OF THE BLOCK USED TO WHICH THE SINE WAVE IS CONNECTED?
@sreedhrk5267
@sreedhrk5267 3 ай бұрын
8
@seenagajula4172
@seenagajula4172 4 ай бұрын
Super explanation sir..🔥
@justintiger9
@justintiger9 4 ай бұрын
Exactly what I needed. Thank you good sir.
@SoujanyaVamaraju-l8p
@SoujanyaVamaraju-l8p 4 ай бұрын
How to measure small resitances
@VarshaSonyHasan
@VarshaSonyHasan 4 ай бұрын
This is too nice
@KushagraShukla-jb5cr
@KushagraShukla-jb5cr 4 ай бұрын
please can you make videos on SV? these were very helpful.....
@janimiyamotivationclasses4669
@janimiyamotivationclasses4669 5 ай бұрын
Contact number please 🎉
@umamaheshwaripatil3396
@umamaheshwaripatil3396 5 ай бұрын
Explained well sir.I liked ur way of explaining.could you please prived a carry save addder behaviour model program?
@SowmyarupaMamilla
@SowmyarupaMamilla 5 ай бұрын
Thanks for giving this kind of vedios thankyou bro
@addielvega
@addielvega 5 ай бұрын
This is behavioral implementation not structural. Behavioral Verilog describes the functionality or behavior of a digital circuit without specifying its internal structure. Structural implementation you are describing the internal structure of the circuit.
@angelmary3691
@angelmary3691 5 ай бұрын
Did you appeared for the entrance exam afrer third year please reply
@knowledgeunlimited
@knowledgeunlimited 5 ай бұрын
Yes.
@angelmary3691
@angelmary3691 5 ай бұрын
How did you prepare what topics are most important we are having it in the next month please give the info
@vikramvicky5110
@vikramvicky5110 6 ай бұрын
How many days after applying did you get the interview call sir?
@knowledgeunlimited
@knowledgeunlimited 6 ай бұрын
In a day only!
@keshavbaldeva5438
@keshavbaldeva5438 6 ай бұрын
setup time can not be negative🙃