sta lec36 - Interview Questions Part1 | static timing analysis tutorial | VLSI
2:27
sta lec36 - Interview Questions Part1 | static timing analysis tutorial | VLSI
Жыл бұрын
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
10:48
PD Lec 67 - Global and Detail Routing | VLSI | Physical Design
Жыл бұрын
PD Lec 66 - Routing Concepts | VLSI | Physical Design
8:20
PD Lec 66 - Routing Concepts | VLSI | Physical Design
Жыл бұрын
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
6:48
PD Lec 65 - Introduction to Routing | VLSI | Physical Design
2 жыл бұрын
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
8:51
PD Lec 64 - Skew Groups | CTS | VLSI | Physical Design
2 жыл бұрын
perl lecture12: data extraction using regular expression | regex | pattern matching
7:04
perl lecture12: data extraction using regular expression | regex | pattern matching
2 жыл бұрын
PD Lec 63 - Post CTS Optimization | VLSI | Physical Design
6:16
PD Lec 63 - Post CTS Optimization | VLSI | Physical Design
2 жыл бұрын
PD Lec 62 - CTS Analysis | VLSI | Physical Design
5:17
PD Lec 62 - CTS Analysis | VLSI | Physical Design
2 жыл бұрын
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
6:06
PD Lec 61 - Crosstalk fixes and prevention | Shielding | NDR | VLSI | Physical Design
2 жыл бұрын
PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
7:24
PD Lec 60 - What is crosstalk ? | CTS | VLSI | Physical Design
2 жыл бұрын
PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design
10:48
PD Lec 59 - Master, Generated and Virtual Clocks | Type of clocks | VLSI | Physical Design
2 жыл бұрын
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
5:46
PD Lec 58 Integrated Clock Gates | ICG | CTS | VLSI | Physical Design
2 жыл бұрын
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
6:21
PD Lec 57 Clock Gate Enable Checks | CGC Paths | CTS | VLSI | Physical Design
2 жыл бұрын
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
10:57
PD Lec 56 Clock Gating Checks | CGC Paths | CTS | VLSI | Physical Design
2 жыл бұрын
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
4:04
PD Lec 55 Power Dissipation in clock tree | Clock gating | CTS | VLSI | Physical Design
2 жыл бұрын
PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design
8:34
PD Lec 54 CTS Exceptions | Float pin | Stop Pin | Exclude Pin | VLSI | Physical Design
2 жыл бұрын
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
9:19
PD Lec 53 CTS Constraints | Spec File | Clock Tree Synthesis | VLSI | Physical Design
2 жыл бұрын
PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design
4:00
PD Lec 52 CTS Algorithms | CTS | Clock Tree Synthesis | VLSI | Physical Design
2 жыл бұрын
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
8:55
PD Lec 51 How to balance skew and latency? | CTS | Clock Tree Synthesis | VLSI | Physical Design
2 жыл бұрын
evolution of Mobile Technology & Cell Phone
6:31
evolution of Mobile Technology & Cell Phone
2 жыл бұрын
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
7:55
PD Lec 50 Clock Tree Synthesis | CTS | VLSI | Physical Design
2 жыл бұрын
PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design
3:41
PD Lec 49 - Introduction to CTS | Clock Tree Synthesis | VLSI | Physical Design
2 жыл бұрын
PD Lec 48-Interview Questions | placement | VLSI | Physical Design
1:09
PD Lec 48-Interview Questions | placement | VLSI | Physical Design
2 жыл бұрын
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
6:34
PD Lec 47 - concurrent clock and data optimization| CCD| Timing | placement | VLSI | Physical Design
2 жыл бұрын
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
6:23
PD Lec 46 - Useful Skew | Timing Fixes in placement | VLSI | Physical Design
2 жыл бұрын
PD Lec 45 - Spare Cells | Physical Only Cells | VLSI | Physical Design
5:54
PD Lec 45 - Spare Cells | Physical Only Cells | VLSI | Physical Design
2 жыл бұрын
PD Lec 44 - Timing Fixes in placement | Part-2 | VLSI | Physical Design
11:15
PD Lec 44 - Timing Fixes in placement | Part-2 | VLSI | Physical Design
2 жыл бұрын
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
7:09
PD Lec 43 - Timing Fixes in placement | Part-1 | VLSI | Physical Design
2 жыл бұрын
PD Lec 42 - SVT LVT HVT Cell variants | VLSI | Physical Design
8:09
PD Lec 42 - SVT LVT HVT Cell variants | VLSI | Physical Design
2 жыл бұрын
Пікірлер
@LuzBryant-h8p
@LuzBryant-h8p Күн бұрын
45202 Alvera Plains
@HarryaJacksona
@HarryaJacksona 2 күн бұрын
Williams William Johnson Deborah Martinez Angela
@veeranjaneyulu811
@veeranjaneyulu811 3 күн бұрын
VLSI academy and VLSI academy
@KelsenBurgess-x7d
@KelsenBurgess-x7d 4 күн бұрын
Robinson Jennifer Perez Jose Thomas Susan
@Ahilan-r2x
@Ahilan-r2x 4 күн бұрын
(w+): Open the file for reading and writing. Truncate it if it exists. If it does not exist, create a new file.
@suuupharshit
@suuupharshit 4 күн бұрын
i tried my best but i can't understand it
@HasnMia-k8s
@HasnMia-k8s 5 күн бұрын
Davis Margaret Thomas Jason White Anthony
@VLSIAcademyhub
@VLSIAcademyhub 5 күн бұрын
What's that?
@lavanyak5268
@lavanyak5268 5 күн бұрын
Bipolar junction transistor means it has 3 different types of materials are placed in form of next to next due to this they its formed two junctions thats why we are calling bipolar junction transistor
@VLSIAcademyhub
@VLSIAcademyhub 5 күн бұрын
Just to clarify it's bipolar because it has carriers in both poles electrons and holes. it uses both electrons and holes (the two types of charge carriers in semiconductors) for its operation.
@lavanyak5268
@lavanyak5268 5 күн бұрын
@@VLSIAcademyhub but in FET also having two charge carriers right. Then why that one calling as UJT (unipolar junction Transistor)
@VLSIAcademyhub
@VLSIAcademyhub 5 күн бұрын
Actually, there’s a bit of a mix-up here. Let me clarify: Field-Effect Transistor (FET): FET is a type of transistor that controls the flow of current by using an electric field. Unlike Bipolar Junction Transistors (BJTs), which use both electrons and holes (bipolar conduction), FETs use only one type of charge carrier: N-channel FET: Uses electrons (negative charge carriers). P-channel FET: Uses holes (positive charge carriers)
@lavanyak5268
@lavanyak5268 5 күн бұрын
​@@VLSIAcademyhub👍
@swapnapujari7532
@swapnapujari7532 7 күн бұрын
Please can you explain why Subtract uncertainty in setup and add in hold what is the reason
@VLSIAcademyhub
@VLSIAcademyhub 5 күн бұрын
This video has explained the very same thing. Can you please tell me if you understand it ? If not what's the doubt ?
@BinduthrayaMatta-xr7tz
@BinduthrayaMatta-xr7tz 10 күн бұрын
Can we print only until some strings that we need using foreach loop?
@VLSIAcademyhub
@VLSIAcademyhub 5 күн бұрын
Yes you can, you have to add some additional code based on your requirement
@abhishekgattupally1727
@abhishekgattupally1727 12 күн бұрын
Thank you can you give ur linkdin id ??
@VLSIAcademyhub
@VLSIAcademyhub 5 күн бұрын
If you search in linkedin VLSI Academy you can find it
@abhishekgattupally1727
@abhishekgattupally1727 14 күн бұрын
The output is " item at 2nd index in list2 is 1 c
@vijayapoojitha3385
@vijayapoojitha3385 15 күн бұрын
Can you please share the slides of the physical design full course and also sta full course,please,helps a lot
@VLSIAcademyhub
@VLSIAcademyhub 14 күн бұрын
There's full static timing analysis related tutorial on our channel please do watch it. It should help you
@Azzubhai047
@Azzubhai047 17 күн бұрын
sir y u told m6 is vertical as well as horizontal in this video
@VLSIAcademyhub
@VLSIAcademyhub 14 күн бұрын
Any metal layer can have only one direction, either horizontal or vertical.
@govindsharma4779
@govindsharma4779 17 күн бұрын
Does this course covers every part of STA for beginners also?
@VLSIAcademyhub
@VLSIAcademyhub 17 күн бұрын
Yes mostly everything is covered
@durgae4974
@durgae4974 17 күн бұрын
What happen if we place power strips before macro placement???
@VLSIAcademyhub
@VLSIAcademyhub 17 күн бұрын
If we you do power grid creation before macro placement then tool will do draw power structure in all places where macros should have sit and you will see lot of pg shorts with macros
@jvsnyc
@jvsnyc 21 күн бұрын
Excellent. I think lappend is the only one of all the list commands covered that modifies the original list. Not all videos make that clear.
@jvsnyc
@jvsnyc 5 күн бұрын
And of course lset
@jvsnyc
@jvsnyc 21 күн бұрын
Extra points for making so clear that each of these commands creates a new list and leaves the old list as it was. Lots of people forget to emphasize that.
@divyamsatle6673
@divyamsatle6673 22 күн бұрын
Gate voltage should be positive incase of PMOS to turn off the transistor.
@devise2641
@devise2641 25 күн бұрын
can anyone help pe why he says that Ep clck is frequncy is high instead of SP frequency
@Problem_Solutions_014
@Problem_Solutions_014 26 күн бұрын
For clkP setup is checked at t = 15 ns because there is a multicycle path. Tool will default check at t = 5 ns next edge Ans: Setup edge number : 4 Hold edge number : 0 (Same concept example is solve at this kzbin.info/www/bejne/jGeVdJKnlJpmpJYsi=kHV_pbKCKpWhZcUF (Playlist video no. sta lec27 timing across clk domains part 1))
@akansharajput_3715
@akansharajput_3715 26 күн бұрын
Thank you so much for your explanation
@jvsnyc
@jvsnyc 27 күн бұрын
Similarly on trimleft it isn't removing a whole string so much as any characters that are anywhere in str2 but come after all chars that are anything but those in str1, like this: % set s1 "Physical Design includes stages from floorplan to routing" Physical Design includes stages from floorplan to routing % set s2 "Physical Design" Physical Design % puts [string trimleft $s1 $s2] udes stages from floorplan to routing
@jvsnyc
@jvsnyc 27 күн бұрын
Great video. There's something about how the trim commands work you didn't quite show, I think. The string of stuff to remove is just a bunch of different characters to be removed if seen at the end, not necessarily a string found at the end. I mean: % set myString $string abcdefccbbaa % string trimright $myString "abc" abcdef Another example: % set s1 "Physical Design includes stages from floorplan to routing" Physical Design includes stages from floorplan to routing % set s2 "Physical Design" Physical Design % puts [string trimright $s1 $s2] Physical Design includes stages from floorplan to rout
@VLSIAcademyhub
@VLSIAcademyhub 26 күн бұрын
Great point!
@jvsnyc
@jvsnyc 27 күн бұрын
It is better and less confusing to call the character '\' as "backslash" and only say "slash" for '/' -- good video tho.
@jvsnyc
@jvsnyc 28 күн бұрын
The arrays you show as continuous actually are just associative arrays that happen to have indexes of "0" "1" "2" "3" etc. -- array names does not necessarily give them in any expected order.
@VLSIAcademyhub
@VLSIAcademyhub 26 күн бұрын
In tcl, if you refer any list by index then it is equivalent to accessing an array by index. If you refer to array by names using array names then it's associative array
@jvsnyc
@jvsnyc 5 күн бұрын
@@VLSIAcademyhub The Tcl Tutorial says: Lists in Tcl are the right data structure to use when you have an arbitrary number of things, and you'd like to access them according to their order in the list. In C, you would use an array. In Tcl, arrays are associative arrays - hash tables, as you'll see in the coming sections. If you want to have a collection of things, and refer to the Nth thing (give me the 10th element in this group of numbers), or go through them in order via foreach, use lists.
@realitycheck....9704
@realitycheck....9704 29 күн бұрын
thankx
@shirindewan878
@shirindewan878 29 күн бұрын
if resistance increases in interconnect , then what will happen @VLSIAcademyhub
@VLSIAcademyhub
@VLSIAcademyhub 26 күн бұрын
If resistance in increase in interconnect then it will lead to increase in interconnect delay, hence overall net delay for that net will increase
@Problem_Solutions_014
@Problem_Solutions_014 Ай бұрын
@ 04:57 The T(uncertainty) = 60ps written
@yashwantht5224
@yashwantht5224 Ай бұрын
Can I get the book link which you have been following
@VLSIAcademyhub
@VLSIAcademyhub 17 күн бұрын
It's based on internet official tcl website
@lucaskindermann2915
@lucaskindermann2915 Ай бұрын
text is blurred in slides 🙁
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
Will try to improve
@jvsnyc
@jvsnyc 27 күн бұрын
@@VLSIAcademyhub I didn't notice it in earlier lessons. In this one, only offered at 360p, some of the text blurs.
@vattirajesh7230
@vattirajesh7230 Ай бұрын
Sir tools explanation we needed
@piyushmohapatra4642
@piyushmohapatra4642 Ай бұрын
For output of the CMOS inverter, Drain of PMOS and NMOS should be connected and output should be taken from that
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
Yes
@travelfreakphani5933
@travelfreakphani5933 Ай бұрын
Super 👌 man 🎉
@piyushmohapatra4642
@piyushmohapatra4642 Ай бұрын
4:04 should be XOR gate for the outputs to toggle
@jeffrinwilfred1887
@jeffrinwilfred1887 27 күн бұрын
exactly i too got same question
@piyushmohapatra4642
@piyushmohapatra4642 27 күн бұрын
@@jeffrinwilfred1887 yep. Don't be confused. What you thought is correct 💯
@travelfreakphani5933
@travelfreakphani5933 Ай бұрын
super mama
@Rahul-hq8gl
@Rahul-hq8gl Ай бұрын
where are interface related paths video ?? where can I find please let me know
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
Interface related paths are explained in static timing analysis section of the channel. There is full STA related tutorial for that on the channel
@magicmuffin1
@magicmuffin1 Ай бұрын
please correct the formulas in your video. Tr =Tclk-Tu Tarrival = tckl-q + tcombo + tsetup
@MohanKumar-m1h
@MohanKumar-m1h Ай бұрын
Is zero skew is possible?
@VLSIAcademyhub
@VLSIAcademyhub 26 күн бұрын
In theory yes and in reality NO And it's not favourable for design to have zero skew
@mercyk6817
@mercyk6817 Ай бұрын
Can u do video sdc file for STA course
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
Sounds good
@RishabhsinghRajput-k6l
@RishabhsinghRajput-k6l Ай бұрын
notes please anyone
@saigithesh3942
@saigithesh3942 Ай бұрын
mcp is just a constraint right? it won't be implemented in design
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
It's a timing constraint, so based on this constraint, physical design for that path is done whenever this is applied
@travelfreakphani5933
@travelfreakphani5933 Ай бұрын
❤
@sanchitgupta2530
@sanchitgupta2530 Ай бұрын
sir has assigned phones according to economic conditions of respective countries...so can understand for imran !
@faizangokak3355
@faizangokak3355 Ай бұрын
To sort the list which consists of collections of integer values. sort() function will consider values in the list as String not the integers values. So sort() function to understand, string to integer values we need to use Space-ship operator i,e. sort {$a <=> $b}. @no = (5,4,3,2,1); print "Original list is : @no "; @sorted_no = sort {$a <=> $b} @no; print "Sorted numbers are: @sorted_no "; Output: Original list is : 5 4 3 2 1 Sorted numbers are: 1 2 3 4 5
@20T109JEFFRYJULIONMETE
@20T109JEFFRYJULIONMETE Ай бұрын
I am joint you company
@nantes9807
@nantes9807 Ай бұрын
Where is LEc 8 sir.
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
kzbin.info/www/bejne/bJzFlaV5oLZnadk
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
This is lec8
@lakshmisrinivasadimulam964
@lakshmisrinivasadimulam964 Ай бұрын
can u please explain for the active low clock check
@Kumar-es2pm
@Kumar-es2pm Ай бұрын
I think Delta between Vih min and vil max should be small to provide good noise margin
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
No delta should be high, if delta is low, means probability of transistor to figure out its high or low is very less.
@kalyan6323
@kalyan6323 Ай бұрын
pls suggest 1 vlsi book for PD students
@VLSIAcademyhub
@VLSIAcademyhub Ай бұрын
For understanding theory of VLSI rabey is good book