[2024-09-15 13:05:44 UTC] iverilog '-Wall' '-g2012' design.sv testbench.sv && unbuffer vvp a.out design.sv:11: syntax error design.sv:11: error: Invalid module item. design.sv:15: warning: implicit definition of wire 'd0'. design.sv:15: warning: implicit definition of wire 'd1'. design.sv:15: warning: implicit definition of wire 's1'. design.sv:16: warning: implicit definition of wire 'd2'. design.sv:16: warning: implicit definition of wire 'd3'. design.sv:17: warning: implicit definition of wire 's0'. Exit code expected: 0, received: 2 Done

behavioral also please

Congratulations 🎉

Sir ,mealey non overlapping wht to do😭😭😭😭😭😭😭, its hard ...not able to understand 😢😢😢

Sir, please mealey non overlapping wht to do sir 😢 , sem end tomorrow 😅... Someone help me😢😢 Sid plssssssssssssss help us

SIRRRRRRRRRRRRRRRRR, NON OVERLAPING PLSSSSSSSSSSSSSSSSSSSSSSSSSS SIR, I HAVE INTERNALS TOMORROW PLSSSSSSSSSSSSSSS SIR

sir can we apply the same trick to both overlapping and non overlapping ??????///

💥💥💥💥

Soopr sir

Good👍

this is the bestttt mooree state diagram tutorial..

Perfect

TY

Thank its really help me

❤️

Can you provide video for non overlapping

Thank you very much! Finally got the concept!

Thanks a lot brother,you gave all required stuff which I really searching for.

Sir please upload more videos on verilog and digital electronics and questions too for bca

Very goog sir Please keep uploading

آپدونوںتوپھرننگےپیرھیگئے ھوںگےگھروںکو😆

😂🙈

Can u explain in english??

how to save the code with particular file name ?

Mast👌

In example 2 we can make 3 grouping ie., 3 pairs( (0,1)(5,13)(8,12))

Thanks you so much sir.. Lot of information u have given for me.. I am from iiit manipur❤❤

thanks sir for the video

I think ismain 9 implicants hone chahiye ek qurds nahi count hua

🧐😄😄😄😄😄😄😄😄

Brother Please upload video as soon as possible, You upload next EDA after months.

😅😅😅😄

thank you. your video solved my all doubts.

Joota maaro inki sir pe

Chor

sir what is that dumpvar s(1) i couldn't get.. that what u said 1arce 0arce.. sir plzz xplain again.

One of the best way to solve these problem.Superb work👍

Understood clearly thank you

can you create playlist for verilog. Easy to understand your videos

Thanks for sharing a wonderful content. Please make videos on System Verilog for implementing the same example

Yes, you can. Even adlec reviera provides you the facility to automatically generated test bench for a verilog module. All you need to purchase the licence and then you can install in your PC. On the other hand EDA playground is a web based application. That can be run on any web browser. No licence is required. Now choice is yours.. all the best.

You have explained it in a very easy way. I really liked the video presentation

Very Nice explanation sir

Thank you so much! You have saved a Brazilian student!

Would you please design this using edaplayground....4:1 using 2:1 mux

Thank you very much sir .Really have got nice help

Nice video sir👍🙏

👍👍

Worth watching...

Nice Sir...