Quine McCluskey, QM Method Part-II
15:23
QM Method with Don't Care Terms
18:01
Пікірлер
@UKing18
@UKing18 Ай бұрын
[2024-09-15 13:05:44 UTC] iverilog '-Wall' '-g2012' design.sv testbench.sv && unbuffer vvp a.out design.sv:11: syntax error design.sv:11: error: Invalid module item. design.sv:15: warning: implicit definition of wire 'd0'. design.sv:15: warning: implicit definition of wire 'd1'. design.sv:15: warning: implicit definition of wire 's1'. design.sv:16: warning: implicit definition of wire 'd2'. design.sv:16: warning: implicit definition of wire 'd3'. design.sv:17: warning: implicit definition of wire 's0'. Exit code expected: 0, received: 2 Done
@63_tanishkgupta55
@63_tanishkgupta55 8 ай бұрын
behavioral also please
@haROBOTus
@haROBOTus Жыл бұрын
Congratulations 🎉
@bruhbruh4137
@bruhbruh4137 Жыл бұрын
Sir ,mealey non overlapping wht to do😭😭😭😭😭😭😭, its hard ...not able to understand 😢😢😢
@bruhbruh4137
@bruhbruh4137 Жыл бұрын
Sir, please mealey non overlapping wht to do sir 😢 , sem end tomorrow 😅... Someone help me😢😢 Sid plssssssssssssss help us
@bruhbruh4137
@bruhbruh4137 Жыл бұрын
SIRRRRRRRRRRRRRRRRR, NON OVERLAPING PLSSSSSSSSSSSSSSSSSSSSSSSSSS SIR, I HAVE INTERNALS TOMORROW PLSSSSSSSSSSSSSSS SIR
@etrixsolutions8126
@etrixsolutions8126 Жыл бұрын
Hi, Yes, you can apply same trick for nonoverlaping case. Note that in nonoverlaping case the machine is always go to the initial state once the sequence has been detected. This is the only difference.
@bruhbruh4137
@bruhbruh4137 Жыл бұрын
sir can we apply the same trick to both overlapping and non overlapping ??????///
@prakashacharya7808
@prakashacharya7808 Жыл бұрын
💥💥💥💥
@rafiq3442
@rafiq3442 Жыл бұрын
Soopr sir
@vikaskumar-ti8jg
@vikaskumar-ti8jg Жыл бұрын
Good👍
@slambergamer91
@slambergamer91 Жыл бұрын
this is the bestttt mooree state diagram tutorial..
@anirbanbanerjee442
@anirbanbanerjee442 Жыл бұрын
Perfect
@lihclore
@lihclore 2 жыл бұрын
TY
@Ankitkumar-yg1wn
@Ankitkumar-yg1wn 2 жыл бұрын
Thank its really help me
@jay12maurya79
@jay12maurya79 2 жыл бұрын
❤️
@abhijitsingh2856
@abhijitsingh2856 2 жыл бұрын
Can you provide video for non overlapping
@praneethan899
@praneethan899 2 жыл бұрын
Thank you very much! Finally got the concept!
@VishvajeetSingh-hc6og
@VishvajeetSingh-hc6og 2 жыл бұрын
Thanks a lot brother,you gave all required stuff which I really searching for.
@Bu0087
@Bu0087 2 жыл бұрын
Sir please upload more videos on verilog and digital electronics and questions too for bca
@etrixsolutions8126
@etrixsolutions8126 2 жыл бұрын
Thanks for watching.. Any specific topic you would like to mention..
@Monu_Rajputra
@Monu_Rajputra 3 жыл бұрын
Very goog sir Please keep uploading
@zahidshakeel8900
@zahidshakeel8900 3 жыл бұрын
آپدونوںتوپھرننگےپیرھیگئے ھوںگےگھروںکو😆
@NasedybhaiYT
@NasedybhaiYT 3 жыл бұрын
😂🙈
@annjohny8763
@annjohny8763 3 жыл бұрын
Can u explain in english??
@dhananjayalum4416
@dhananjayalum4416 3 жыл бұрын
how to save the code with particular file name ?
@etrixsolutions8126
@etrixsolutions8126 3 жыл бұрын
Once you open a new playground. there is option named share in the lower window. Here you can name your design and save it in the EDA playground data base. you can make it private or publish it. To access that saved design click on the playgrounds tab available at top right corner near the profile tab. in the playgrounds tab you can find all the design saved by you. hope you got the answer. thanx for watching.
@dhananjayalum4416
@dhananjayalum4416 3 жыл бұрын
@@etrixsolutions8126 yaaa tq for ur reply and I resolved my issue 😊
@Mytime.295
@Mytime.295 3 жыл бұрын
Mast👌
@vustudy6720
@vustudy6720 3 жыл бұрын
In example 2 we can make 3 grouping ie., 3 pairs( (0,1)(5,13)(8,12))
@chandunukala7279
@chandunukala7279 3 жыл бұрын
Thanks you so much sir.. Lot of information u have given for me.. I am from iiit manipur❤❤
@yashwanthnamburi3824
@yashwanthnamburi3824 3 жыл бұрын
thanks sir for the video
@arshverma8072
@arshverma8072 3 жыл бұрын
I think ismain 9 implicants hone chahiye ek qurds nahi count hua
@kondlepurajini2579
@kondlepurajini2579 3 жыл бұрын
🧐😄😄😄😄😄😄😄😄
@amirsharfu
@amirsharfu 3 жыл бұрын
Brother Please upload video as soon as possible, You upload next EDA after months.
@kalayyah9102
@kalayyah9102 3 жыл бұрын
😅😅😅😄
@rutvikjr8251
@rutvikjr8251 3 жыл бұрын
thank you. your video solved my all doubts.
@rahulsurve1438
@rahulsurve1438 3 жыл бұрын
Joota maaro inki sir pe
@sabbirrahaman572
@sabbirrahaman572 3 жыл бұрын
Chor
@jayshreepatra1834
@jayshreepatra1834 3 жыл бұрын
sir what is that dumpvar s(1) i couldn't get.. that what u said 1arce 0arce.. sir plzz xplain again.
@etrixsolutions8126
@etrixsolutions8126 3 жыл бұрын
Hi, If you are doing the hierarchical design, in which the main module is decomposed in submodules. Then during the simulation if you want to display the signals of only main module then use (1). Similarly to display the signals of second level hierarchy, use (2). For all level of hierarchy use (0). Sorry for late response. Thanks for watching the video. Please subscribe the channel.
@tanmaythakare638
@tanmaythakare638 3 жыл бұрын
One of the best way to solve these problem.Superb work👍
@selinsam2005
@selinsam2005 4 жыл бұрын
Understood clearly thank you
@pawan85285
@pawan85285 4 жыл бұрын
can you create playlist for verilog. Easy to understand your videos
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Ya sure.. I am working on it.
@AjinkyaMahajan
@AjinkyaMahajan 4 жыл бұрын
Thanks for sharing a wonderful content. Please make videos on System Verilog for implementing the same example
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Thanks for your valuable feedback. We will publish a video on your demand very soon.
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Yes, you can. Even adlec reviera provides you the facility to automatically generated test bench for a verilog module. All you need to purchase the licence and then you can install in your PC. On the other hand EDA playground is a web based application. That can be run on any web browser. No licence is required. Now choice is yours.. all the best.
@cookstorybyvibha5580
@cookstorybyvibha5580 4 жыл бұрын
You have explained it in a very easy way. I really liked the video presentation
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Thanks for your valuable words.
@bobo_for_all
@bobo_for_all 4 жыл бұрын
Very Nice explanation sir
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Thanks dear..
@felipeguimaraes2568
@felipeguimaraes2568 4 жыл бұрын
Thank you so much! You have saved a Brazilian student!
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Thanks, glad to know that I helped you. Stay connected for more such videos.
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Just wanted to know that how this video can save someone?
@felipeguimaraes2568
@felipeguimaraes2568 4 жыл бұрын
@@etrixsolutions8126 I'm doing a verilog homework, but my professor's examples wasn't good as yours. I wasn't understanding how to work with EDA and Verilog. Now, I'm already finishing my work! Thanks!
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Check this for more examples. kzbin.info/www/bejne/nH2aqIZvbqd0mNk
@praveennayak6486
@praveennayak6486 4 жыл бұрын
Would you please design this using edaplayground....4:1 using 2:1 mux
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Yes, we can.. I will publish a video on your demand very soon.
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
kzbin.info/www/bejne/nH2aqIZvbqd0mNk On demand, EDA playground tutorial 4to1 using 2to1 mux
@praveennayak6486
@praveennayak6486 4 жыл бұрын
Thank you very much sir .Really have got nice help
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
My pleasure.. thanks for the feedback
@piyushchandak2384
@piyushchandak2384 4 жыл бұрын
Nice video sir👍🙏
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Thanks dear, stay connected for more such videos.
@piyushchandak2384
@piyushchandak2384 4 жыл бұрын
👍👍
@rakhigupta6368
@rakhigupta6368 4 жыл бұрын
Worth watching...
@SumitSharma-wf6qo
@SumitSharma-wf6qo 4 жыл бұрын
Nice Sir...
@etrixsolutions8126
@etrixsolutions8126 4 жыл бұрын
Thanks dear..