Normally high dv/dt nodes coupling via parasitic capacitances to earth lead to common mode noise. High di/dt would too but the coupling mechanism would be different.

Indeed, I've have found them to be a great choice in many applications now. It is amazing the capability you can get these days

I’d suggest finding an area you are interested in as a starting point and then seeing what options you have.

Thanks Terry for taking the time to feedback here. Noted regarding the use of music, useful input. I'm not sure yet if people prefer to have this or not, maybe for educational stuff, without is best. I'll leave it off the next video and see how folks respond.

​@@ElectronicmindsUK yes please, it is very distracting, the transients from the rhythms interfere with the transients of your speech and it makes listening difficult (and tiring), thank you 🙏🏻

Thanks Mohamed, ok we’ll leave it off the next one. Hope the content is interesting for you.

I’m sorry but I don’t know. I believe you can define your own materials though from the underlying magnetic properties. Good luck!

@@ElectronicmindsUK I am just wondering why it is not included in the Library,i thought it is allready a common material.Thanks for the fast answer.

Yes, the peak current during the gate drive transitions comes largely from the ceramic decoupling capacitance we use both on the dcdc output and local to the gate driver IC. The isolated dcdc really just responds to the average current since the peaks are so short.

Thanks for your feedback and good to hear that this was useful for you. We are working on a different set of videos now but will put your request onto our list for future ideas. Many thanks!

Thanks for your question and apologies for the delay in replying. Yes, the miller effect can induce parasitic turn on in both the low side and high side devices. The mechanism is the same. I hope you enjoy the rest of the content here.

Sure, please let me know your email and I will send you a copy.

Well spotted! It is a great platform for experiments.

Thanks for your great feedback. What sort of gate drive protection mechanisms are you interested in most?

@@ElectronicmindsUK hey guys sorry for the late reply To be honest if you could do the following that would mean the world to me 1. Overcurrent Protection (OCP) 2. Short-Circuit Protection (SCP) 3. Under-Voltage Lockout (UVLO) 4. Over-Voltage Protection (OVP) 5. Thermal Protection 6. Desaturation Protection (DESAT) 7. Dead-Time Protection 8. Phase Loss Protection 9. Reverse Voltage Protection I know that’s allot of material so that being said 123456 are by far the most important. Worked schematic examples of each would also be amazing

Hey guys, Just wanted to check in to see if this is something that you would still be interested in doing a video on. I understand there were allot of protection systems listed. I think an episode that focuses on the major protection mechanisms used in industry with some accompanying circuit simulation would be awesome. There’s not that much gate drive protection videos online and the few that are are pretty poor in my opinion. Thanks for the excellent series, it’s really helped me gain knowledge in power electronics Doron

We used an impedance bridge, in our case the Keysight 4263B. It measures the real part of the impedance (I.e. the resistance at a few spot frequencies including 100kHz). Keep in mind that the measurement is only small signal so won’t necessarily capture non-linear losses such as the increase in loss with Bpeak.

@@ElectronicmindsUK Thank You for that. I am using Bode100 (from omicron labs) for the impedance measurement I am still unable to measure ac resistance accurately

The process would be similar to other gate drive designs, you need to set the drive voltage levels (uni-polar or bi-polar), drive strength etc and work out the power requirements of the gate driver - these often scale with frequency. 400kHz PWM is a time period of only 2.5us so you also will want to ensure good drive strength to keep edges as sharp as possible and minimise miller induced effects. The design of the gate drive will depend on the type of device you are driving too.

The value of CM Choke will depend on many aspects of the design and it is hard to give accurate guidance on this. However, as a good starting point, for offline isolated supplies up to about 100W, typical values are around 10mH. Start with that and then test/iterate. Remember that the CM choke (and any inductor) is only inductive over a specific range of operating frequencies. For your example of the CM Choke on a shunt resistor, this maybe to attenuate CM noise from the power stage (shunt) reaching the control board. CM noise is an interesting thing. It will find its way through all the parasitic elements of your design (i.e. the bits which you might not know are there) and it is key to understand the dominant coupling paths.

If you can synchronise the ADC sampling to the PWM (or an integer fraction of it) then it is possible to sometimes avoid ADC sampling during a switching transition. This can help to reduce noise. If you sample asynchronously then you can end up getting beat frequencies appearing in your sampled data.

Yes, we plan to start some more in the next few months so please check back in to see what we have

THX @@ElectronicmindsUK

Here is the user manual link, it’s all covered in there www.femm.info/Archives/doc/manual42.pdf

Tab key

Do you mean power factor here or something else?

Hi Aidan, thanks for your detailed comments. Great to see you have been playing with FEMM, especially since you are modelling an LLC. this is a great topology and we are building one at the moment too. Watch out for deltaB in your magnetics, we have found that the dominant loss mechanism in our the converter is core loss. For the ETD, I can see the problem you have in that the centre leg is round in cross-section which does make it rather hard to model in a 2D tool. I've not looked into trying to model these style cores and i think you correct that 2D tools such as FEMM will struggle. Maybe you could approximate the centre leg by modifying it to be a square cross-section instead with the same x-sectional area? This should give a reasonably good approximation but depends how detailed you want your modelling to be (fringing etc will not be correct). To do this accurately you probably need a 3D tool such as Comsol but I've not had any experience myself with that. Still, as a free tool, you can do a lot with 2D FEMM.

Thanks Ian, It seems we came to the same conclusion. I either try and approximate the centre leg by adapting its width to more effectively represent the cross-sectional area, or I stick with using a square section core. I have built a couple of LLCs already at lower power levels ~200W and hand-calculated and iterated. This time however I am aiming at >1kW and it is starting to look like I need to model closer to reality as things are likely to get both expensive and hot if I get it wrong. However thanks for your helpful comments.

You are most welcome, check out the rest of our series since we have lots of other power electronics stuff covered there.

Thanks for this great feedback! It is really valuable to hear how we can improve our videos so thanks for taking the time to make these suggestions!

Thanks for the feedback Martin, much appreciated!

The definition of skin depth is the distance into the conductor cross section where the current density falls to 1/e of that at the surface. You can't really avoid it but you can see that running a conductor with radius greater than the skin depth (i.e. diameter of twice the skin depth) means that very little of the current flows in the centre as the current density drops exponentially. We use 2x the skin depth for the diameter as a good starting point.

Thanks very much for your kind feedback. Immersion cooling of PE is a really interesting approach but not one I have practical experience with. What I think it will do is provide significantly improved heat transfer, especially from components which are harder to cool (e.g. magnetic parts). One interesting thing to consider is that the liquid is just a heat transfer mechanism so you will still need a way to couple heat out from the liquid and into the local ambient. There are some fluids from 3M which look interesting www.3m.co.uk/3M/en_GB/novec-uk/applications/thermal-management/immersion-cooling-of-power-electronics/#:~:text=Immersion%20cooling%20involves%20putting%20electronics,into%20the%20heat%20transfer%20fluid.

Good question! I've not modelled permanent magnets myself with FEMM but there are some examples online of people doing this. Take a look at www.femm.info/wiki/PermanentMagnetExample. There are some other guides which cover modelling laminates in FEMM, take a look at www.femm.info/wiki/onedge

The focus of this video is to translate a set of electrical requirements for a magnetic component into a physical design (core, gap, turns etc). The justification for those electrical requirements comes from how the power stage itself is designed. In the case of the flyback converter example here, we do cover the topology design which leads to the electrical requirements of the magnetics in one of our other videos. Take a look at kzbin.info/www/bejne/fKe6qpSZjdqXlac

Glad to hear that you liked the content! If you remove the PE wire then the common-mode noise will find it harder in the lower frequency ranges to find its way to the LISN. However, there are lots of other parasitic paths, mainly capacitive which will allow common-mode current to find its way back to the LISN and get registered. So removing the PE wire will most likely reduce the levels you see but the spectrum will still contain CM noise. You can achieve a better result using splitters to isolate DM and CM noise, check out this link www.analog.com/en/analog-dialogue/articles/separating-common-mode-and-differential-mode-emissions-in-conducted-emissions-testing.html

We found that you can model in two main ways in FEMM, either define a composite area which you then specify a number of turns to contain or draw them individually. Mostly the composite approach works well enough.

Sorry, not presently

Thanks for your feedback!

Hello, thanks for your question. We didn't use any special techniques here for the PLECs simulation other than the fact that during simulation we gradually changed one of the feedback capacitors to decrease the phase margin. We did this in a few steps as the simulation ran to show the transient response behaviour of the system as we move from a stable design towards one which is unstable. The simulation still runs in the unstable case but just shows an output behaviour which is oscillatory and doesn't recover from the transient load step. The same effect would happen in real systems whereby systems with small phase margins show many oscillatory cycles before settling after a transient and unstable systems continue to oscillate. I've not played with PSIM before but would be interested in how it compares to the simulations in this webinar!

You are most welcome, great to hear it was useful!

I'll take a look at the video for you. If it is laggy like you say then I'll check the settings on how it was recorded as it maybe too compressed perhaps.

You are lucky to be taking courses with these professors Rahul!

Thanks for the comment. VOR is a primary side referenced value and is the same with multiple output flybacks. With multiple outputs, you have multiple secondary windings. In each case, the VOR is approximately Np*Vo/Ns where Vo is the output voltage each output and Ns is the number of turns of the respective output winding. Higher outputs have more secondary turns and the primary referenced VOR remains the same. I hope my explanation makes sense.

I have them available but not sure I can attached them here?

@@ElectronicmindsUK yes, that would be helpful. Thanks

We have experimented with exactly that and I believe it does help. I don't have any data yet to confirm this though.

Glad you found it useful. Sorry but we don't release the notes or MathCAD files presently.

The source of the common mode current is anything which can result in current flowing in earth. In isolated supplies, we tend to look at the common-mode current generated from a fast edge on the primary winding coupling current into the secondary and also the cooling tabs of power transistors coupling noise from fast moving drain nodes onto heatsinks. Both these mechanisms ultimately couple current into earth via parasitic capacitances. It is also why sometimes earthing heatsinks directly can provide a direct path for common-mode current flow.