UVM CLASS HIERARCHY
14:30
4 жыл бұрын
uvm testench architecture
31:45
5 жыл бұрын
Static Properties and Methods 1
24:22
Data Hiding and Encapsulation 2
26:36
Data Hiding and Encapsulation 1
15:02
Oops in system verilog 2
44:34
6 жыл бұрын
Oops in system verilog 1
36:39
6 жыл бұрын
SV verification environment
15:11
6 жыл бұрын
polymorphism sv
18:43
7 жыл бұрын
Пікірлер
@ffgammerpro609
@ffgammerpro609 2 ай бұрын
what is mean by abstract class . if uvm_void does not contains any data members or methods . then get_config and find_all is what
@tanjirotv3942
@tanjirotv3942 4 ай бұрын
plz improve audio quality its very bad
@PrashanthsVlog
@PrashanthsVlog 5 ай бұрын
Thank you sir and why not uploading any video related uvm sir please do
@sumitkumarvishwakarma327
@sumitkumarvishwakarma327 5 ай бұрын
Great Explanation Sir.
@vishalgowtham896
@vishalgowtham896 5 ай бұрын
VERY NICE AND USEFUL CONTENT , BUT your voice quality is poor
@ChiragHadiya
@ChiragHadiya 10 ай бұрын
Nice explanation.
@sunnykvofm
@sunnykvofm 11 ай бұрын
please share slides
@bajantrisivasai6344
@bajantrisivasai6344 Жыл бұрын
definitions are very easy to explain...
@LulusCastle
@LulusCastle Жыл бұрын
Voice☹️😔
@elcademy4241
@elcademy4241 Жыл бұрын
Very informative but could you please use proper mic from next time?
@politicalandhra
@politicalandhra 2 жыл бұрын
super explaination sir
@electricalspeed8021
@electricalspeed8021 2 жыл бұрын
Thank you sir
@silicon_talks
@silicon_talks 2 жыл бұрын
great videos
@rockingstone7700
@rockingstone7700 2 жыл бұрын
perfectly explained .......to the point
@krishnavarasala5196
@krishnavarasala5196 2 жыл бұрын
Thank you,explained very well, useful content but voice quality should be improved
@sankasuvarna1764
@sankasuvarna1764 2 жыл бұрын
Life saviour sir u r videos really today gone through ur all videos superb but y did u stopped uploading sir pls upload sir no one else can explain in this much deep way pls upload all videos of sv,uvm pls pls
@sankasuvarna1764
@sankasuvarna1764 2 жыл бұрын
U r god to me serioulsy explaines every single word menaing loveed ur tutorial expecting all videos of sv and uvm in the same way...really hats off to ur patienece and dedication best ever tutorial in youtube
@mohammadfurqan9343
@mohammadfurqan9343 2 жыл бұрын
UVM Sequence_item class is not a component
@gauravsrivastav2339
@gauravsrivastav2339 2 жыл бұрын
In polymorphism example, we can skip the object creation for parent class. In which case it is necessary to have the object creation for parent class as well?
@優さん-n7m
@優さん-n7m 3 жыл бұрын
oops, how did I end up here
@prabhudayal4687
@prabhudayal4687 3 жыл бұрын
upload more videos on uvm
@vlsiforfreshers7449
@vlsiforfreshers7449 3 жыл бұрын
Sure
@prabhudayal4687
@prabhudayal4687 3 жыл бұрын
explanation is good
@prabhudayal4687
@prabhudayal4687 3 жыл бұрын
explained very well but technical aspect also required
@vlsiforfreshers7449
@vlsiforfreshers7449 3 жыл бұрын
Yes we are going to upload more videos which will cover it completely
@neerajpandey1347
@neerajpandey1347 3 жыл бұрын
Great job sir
@vlsiforfreshers7449
@vlsiforfreshers7449 3 жыл бұрын
Thanks neeraj sir
@pgproyt4366
@pgproyt4366 3 жыл бұрын
It's very useful to us
@vlsiforfreshers7449
@vlsiforfreshers7449 3 жыл бұрын
Thanks PG Pro yt
@alfiyashaikh3754
@alfiyashaikh3754 3 жыл бұрын
Can u please tell me in cadence while designing gates what does P_18_mm and N_18_mm means??
@swaratpal4105
@swaratpal4105 3 жыл бұрын
Plzz upload more videos of SV and UVM, great explanation.
@mughahotoyeptho1615
@mughahotoyeptho1615 3 жыл бұрын
Sir please update the video lecture series..for other topics aswell Your explanation is simple and very understandable one. Appreciating your way of teaching
@mughahotoyeptho1615
@mughahotoyeptho1615 3 жыл бұрын
So satisfying lecture.. tq sir
@alekhyadevi8169
@alekhyadevi8169 3 жыл бұрын
very nice sir understood crystal clear can you plz upload more topics
@maheswarreddy4394
@maheswarreddy4394 4 жыл бұрын
More noise ... not a clear voice..
@rameshbabuchintala2002
@rameshbabuchintala2002 4 жыл бұрын
Nice explanation! Waiting for more videos.
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Thanks..
@gramvikasfoundation960
@gramvikasfoundation960 4 жыл бұрын
Absolutely wonderful and fabulous explanation.. Thank you so much your teaching way is so amazing. Please make videos on next topic of uvm...
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Thanks @Jitander Rawat
@tausid979
@tausid979 4 жыл бұрын
Sir why we need uvm_void base classes if it does not have any functionality inside the base classes , I mean what is objectives to have uvm_void classes ?
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Taushid it's true that if we will derive a class from UVM void it does'nt have any UVM functionality but still it allows to create some generic container of objects..
@tausid979
@tausid979 4 жыл бұрын
@@vlsiforfreshers7449 okay sir....will see in your upcoming videos how you will use uvm_void in examples while teaching us, Thanks
@ffgammerpro609
@ffgammerpro609 2 ай бұрын
@@vlsiforfreshers7449 what is mean by generic container of object
@sahilagarwal8555
@sahilagarwal8555 4 жыл бұрын
Sir can you make a course on System verilog? I know verilog but haven't started with SV.
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Just visit my channel once there you will get few videos on system verilog which I have already uploaded and I working on the remaining stuff also..
@sahilagarwal8555
@sahilagarwal8555 4 жыл бұрын
Sir the audio quality is not so good in those videos😅
@navneetjha6887
@navneetjha6887 4 жыл бұрын
👍
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Thanks @Navneet Jha..
@naveen7282
@naveen7282 4 жыл бұрын
🔥👍
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Thanks caul..
@coding_vlsi_vietnam
@coding_vlsi_vietnam 4 жыл бұрын
*VERY HELP FULL !!!! THANKS FOR YOUR UPLOAD*
@rk19mks85
@rk19mks85 4 жыл бұрын
Helpful !!! Summary starts at @27 : 30
@rasagnasaranga1405
@rasagnasaranga1405 4 жыл бұрын
Sir make videos on all topics of uvm
@ayus_sh
@ayus_sh 4 жыл бұрын
Respected Mohan sir , please upload more videos on system verilog. It is really helpful for freshers in building good concepts. Please help us sir.
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Thanks Ayush. Sure I will upload more videos. Right now I am working on n the stuff.
@deepakkumar-fh5sq
@deepakkumar-fh5sq 4 жыл бұрын
Amazing, class is totally understood 👍
@vlsiforfreshers7449
@vlsiforfreshers7449 4 жыл бұрын
Thanks Deepak..
@gramvikasfoundation960
@gramvikasfoundation960 5 жыл бұрын
It's really very helpful Thank-you sir for uploading Please make video on next topic
@sushreeanusmitasahu7651
@sushreeanusmitasahu7651 5 жыл бұрын
Sir, it was an amazing explainations on sv. It will be very much helpful if u make videos on complete uvm explainations. Thank you sir.
@karthikarthik3455
@karthikarthik3455 5 жыл бұрын
Thanks for your video it's great explanation
@vlsiforfreshers7449
@vlsiforfreshers7449 5 жыл бұрын
Thanks
@poojadevi-ok1qk
@poojadevi-ok1qk 5 жыл бұрын
Hi sir... Yiur video are very awse.. get i get ur email id..
@kushalsonkar6023
@kushalsonkar6023 5 жыл бұрын
well explained.
@suniludvanshi28
@suniludvanshi28 5 жыл бұрын
Good mohan...
@muhammadsaleemkottupanthar2321
@muhammadsaleemkottupanthar2321 6 жыл бұрын
Sir, you have changed the task name of parent(super) class only by adding virtual, not changed child task name. Shall we change both or parent only?. Which is better way?
@itsabhijeetanand
@itsabhijeetanand 6 жыл бұрын
sir ,will u plz post all videos of system verilog
@swethareddy1304
@swethareddy1304 6 жыл бұрын
pls upload coverage videos