Machine Learning on FPGAs: Exercises
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Video Streaming for FPGA Remote Lab
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@saleem_22-f7i
@saleem_22-f7i 27 күн бұрын
It would be incredibly helpful if you could create a video tutorial or walkthrough on the FPGA implementation of a classification model, particularly focusing on the Naive Bayes Classifier. If you have any resources, such as Verilog code examples, design materials, or related documents, I would sincerely appreciate it if you could share them.
@marcowinzker3682
@marcowinzker3682 25 күн бұрын
Thank you for the suggestion. That might be a topic for a student project. But I don't have information I can share at this moment.
@dr.rezwanurrahman336
@dr.rezwanurrahman336 Ай бұрын
Awesome! This is very helpful and thank you, Prof. Dr. Marco Winzker!
@siddusyave9566
@siddusyave9566 Ай бұрын
Which software is used to automatically generate vhdl code professor
@marcowinzker3682
@marcowinzker3682 Ай бұрын
The software is Octave. But please note, this is not a general purpose automatic translation from a problem description to VHDL code. The code generation is for the parameter of the machine learning training to the neural network.
@siddusyave9566
@siddusyave9566 Ай бұрын
Thanks for your reply
@siddusyave9566
@siddusyave9566 Ай бұрын
As a beginner which hardware language is best to learn vhdl or systemverilog professor
@marcowinzker3682
@marcowinzker3682 Ай бұрын
@@siddusyave9566 Both are good. See if you can find someone in your institution (university? company?) who can give you advice on starting with the language.
@vardhitveeramachaneni8173
@vardhitveeramachaneni8173 3 ай бұрын
Amazing, I plan to implement on Max10 FPGA. Will the computational resources be sufficient?
@marcowinzker3682
@marcowinzker3682 3 ай бұрын
Best thing to do: Try it out by downloading the code and doing FPGA synthesis. The check computational resources, you can make a test run without pin constraints.
@fc3fc354
@fc3fc354 3 ай бұрын
Hi , I wanted to ask something Since the we will deploy the NN in FPGA to store th data persistency of the training and predicting shouldnt we convert the training images in a fixed point representation ?
@marcowinzker3682
@marcowinzker3682 3 ай бұрын
Hi, the training images do not go into the FPGA. They are used to determine the parameters and the parameters go into the FPGA.
@fc3fc354
@fc3fc354 3 ай бұрын
@@marcowinzker3682 sorry maybe we misunderstood each other Once the parameters have been calculated( the parameters have been defined on base of the input images) , then at inference time when the fpga gets the image data(after it has been trained) and goes on the forward propagation , is it bad if we took the images as double while in fpga they will be processed as fixed points?
@marcowinzker3682
@marcowinzker3682 3 ай бұрын
@@fc3fc354 There is research on doing machine learning applications without high precision arithmetic. Of course there are small differences if you do floating point or fixed point with 32, 16, 8 bit accuracy. Often 8 bit accuracy gives good results with acceptable hardware effort.
@ehabal8781
@ehabal8781 4 ай бұрын
Hi Doctor Can please suggest phd topic based on Vhdl research
@marcowinzker3682
@marcowinzker3682 4 ай бұрын
I regret, I can not provide individual tuition or consulting.
@clementsu5340
@clementsu5340 4 ай бұрын
Thank you Dr. Winzker! This video series has been very helpful for my self-learning!
@DuongNguyen-wz6uc
@DuongNguyen-wz6uc 5 ай бұрын
Sir, I have a few question about machine learning on fpga , can I connect with you by using email ? Thank you , Sir
@marcowinzker3682
@marcowinzker3682 5 ай бұрын
I regret, I can not provide individual tuition or consulting. Nevertheless, I try to answer specific question to the video lectures.
@subhajitdas6470
@subhajitdas6470 6 ай бұрын
Very useful information...
@nguyendat3335
@nguyendat3335 6 ай бұрын
Hello professor, I set NetworkStructure as [3 7 7 2] on Octave and ran the simulation and got wrong results, after debugging I found that octave was generating more number of Weight than needed, specifically is that with setting [3 7 7 2] , the correct number of Weight should is 100 but now it is 107. Dear Professor, please give me a suggestion regarding this problem
@nguyendat3335
@nguyendat3335 6 ай бұрын
Dear proffesor, when increase the hidden layer, do we need to change the delay of the luminance level? I ran with two hidden layers, networkStructure is [3 7 7 2] and change connection[ ] to correspond to the output of NN but the result is not correct
@marcowinzker3682
@marcowinzker3682 6 ай бұрын
Yes, you have to adapt the delay of the luminance. The neuron has a delay of 4 (?) cycles, so an additional layer increases the delay of the neural network by this number of cycles. I made a question mark behind the "4", because I have not verified this number. I'm 90% sure, but it could be 1 cycle more or less.
@theoryandapplication7197
@theoryandapplication7197 6 ай бұрын
useful information , best wishes brother
@bidyutbikashborah800
@bidyutbikashborah800 6 ай бұрын
Sir can i get access to FPGA Vision Open -Online Course, i am from Tezpur University, Assam India
@marcowinzker3682
@marcowinzker3682 6 ай бұрын
The course in 2024 is nearly completed. The next course will be 2025.
@ieadieade
@ieadieade 6 ай бұрын
When will it be starting
@marcowinzker3682
@marcowinzker3682 6 ай бұрын
It is always mid April to mid June. Announcements will be on our webpage "FPGA Vision Open Online Course".
@bidyutbikashborah800
@bidyutbikashborah800 6 ай бұрын
@@marcowinzker3682 is there any provision or way to get online materials. Waiting till 2025 is very hard😊.
@udayatejwani9572
@udayatejwani9572 6 ай бұрын
Hi. How much is the tuition fee?
@ostrov11
@ostrov11 6 ай бұрын
... молодцом.
@squeakytoyrecords1702
@squeakytoyrecords1702 6 ай бұрын
You hit this one out of the park!! Well done, Thank you.
@KraiemRayene
@KraiemRayene 7 ай бұрын
hello, can you send me the dataset folder you used for the shape recongnition application, please ?
@marcowinzker3682
@marcowinzker3682 7 ай бұрын
The data is in GitHub: github.com/Marco-Winzker/NN_Pattern_FPGA Go to: Octave, samples_png
@KraiemRayene
@KraiemRayene 7 ай бұрын
@@marcowinzker3682 thank you very much for your help.Can I use these datasets on matlab
@marcowinzker3682
@marcowinzker3682 7 ай бұрын
@@KraiemRayene Sure.
@KraiemRayene
@KraiemRayene 7 ай бұрын
@@marcowinzker3682 thank you
@muhammedfayas5907
@muhammedfayas5907 7 ай бұрын
SIr, Do you know how to access the biult in FPGA block RAM and store the text file?
@marcowinzker3682
@marcowinzker3682 7 ай бұрын
Please have a look at the video "Machine Learning on FPGAs: Sigmoid Function and Exercises". The sigmoid function is implemented with a built-in block RAM. kzbin.info/www/bejne/mqrKq6V4nql5pM0
@jnestor481
@jnestor481 7 ай бұрын
Great video
@sanikathorbole175
@sanikathorbole175 7 ай бұрын
sir why VHDL and not verilog? Any significant reason?
@marcowinzker3682
@marcowinzker3682 7 ай бұрын
No reason. Both languages are fine.
@theoryandapplication7197
@theoryandapplication7197 7 ай бұрын
thank you sir the video that i am looking for
@yihuang200
@yihuang200 8 ай бұрын
professor, is it fine if i change the raspberry Pi into my own laptop as the HDMI input? the result of the HDMI receiver software shows lots of read/write fails after i try it. What should i do?
@marcowinzker3682
@marcowinzker3682 8 ай бұрын
Yes, you can use another HDMI source. I only checked the setup with the Raspberry Pi and 720p video format. For your error messages, i have two assumptions: a) The video format is unknown. Try 720p@60Hz (1280x720 pixel). b) There is a problem with the interconnection. Try another cable and another laptop (from a friend).
@yihuang200
@yihuang200 8 ай бұрын
@@marcowinzker3682 Sure, I'll try it, thanks for the assumptions. By the way, the window of the HDMI receiver's software shows like below: HDMI-RX [TERASIC-00000.001]RX hardware Reset I2C Read Fail: Address+1 NACK! I2C Write Fail: SubAddress NACK! [TERASIC-00000.075]write eeporm-0 fail I2C Read Fail: Address+1 NACK! I2C Write Fail: SubAddress NACK! [TERASIC-00000.092]write eeporm-1 fail I2C Read Fail: Address NACK! I2C Read Fail: Address NACK! I2C Read Fail: Address NACK! I2C Write Fail: Address NACK! I2C Write Fail: Address NACK! I2C Read Fail: Address NACK! I2C Read Fail: Address NACK! I2C Write Fail: Address NACK! Please help me with it, thanks.
@marcowinzker3682
@marcowinzker3682 8 ай бұрын
@@yihuang200 It seems, there is no connection. Maybe the design of the FPGA is not correct. Do you have correct pin assignments? Did you import of the constraints?
@yihuang200
@yihuang200 7 ай бұрын
@@marcowinzker3682 Sir, can you update the files again? thanks!
@marcowinzker3682
@marcowinzker3682 7 ай бұрын
Yes, I did an update: magentacloud.de/s/GjKTHr2GQazibNf
@FacundoMartinKolosSuarez
@FacundoMartinKolosSuarez 8 ай бұрын
Dear Sir I've compiled and started the lane detection and I'm experiencing a strange problem: The lane detection image it's partially displaced to the right. Also I tested with other images, and the resulting image it's only showing a half of the original image. The other half it's showing only white. Many thanks in advance.
@marcowinzker3682
@marcowinzker3682 8 ай бұрын
Interesting. The solution depends on the board you are using (the remote lab? your own board?) and the displacement. So, displacement can be a) the left half of the image is white and the right half is in the correct position or b) the image is shifted to the right and the left edge of the image is in the center of the screen. a) would be an error in signal processing, like overflow, incorrect wordwidth, ROM not found b) would be a sync error, maybe HS is inverted
@FacundoMartinKolosSuarez
@FacundoMartinKolosSuarez 8 ай бұрын
@@marcowinzker3682 The displacement that I experience it comes when I execute the C code with the sample image, I'm not using the board in this moment.
@theoryandapplication7197
@theoryandapplication7197 8 ай бұрын
thank you sir it is very useful
@edbertkwesi4931
@edbertkwesi4931 8 ай бұрын
really amazing
@AmirabasBiy98
@AmirabasBiy98 8 ай бұрын
Hi prof, please implement a neural network of xor in vhdl. Thank you.
@marcowinzker3682
@marcowinzker3682 8 ай бұрын
Interesting question! As the neural network has a hidden layer, an xor should be no problem. You could use training data with xor-characteristics and see how training handles that. I will also have a look into it.
@AmirabasBiy98
@AmirabasBiy98 8 ай бұрын
@@marcowinzker3682 for an xor NN we have weights and 2 biases and input data 00,01,10,11. In fact I have a trained NN , now I wanna implement it in vhdl. I think we have to write a package for each neuron. Please let me know. thanks a lot.
@wachirakaburu2332
@wachirakaburu2332 8 ай бұрын
Hey prof. I'm also interested in the implementation of a neutral network in FPGA. In fact I would like to know how generate VHDL code a particular trained neural network. I'm looking forward to hearing from you
@marcowinzker3682
@marcowinzker3682 8 ай бұрын
@@wachirakaburu2332 The video "Machine Learning on FPGAs: Advanced VHDL Implementation" explains VHDL generation from Octave. kzbin.info/www/bejne/eaDcmXSnirhlnJI
@Abdulbuzdar1
@Abdulbuzdar1 8 ай бұрын
Thanks sharing this tutorial. Please make more videos on explaining the code in detail and VHDL basics tutorial.
@marcowinzker3682
@marcowinzker3682 8 ай бұрын
For explaining the code in detail, please have a look at the other videos in the playlist, e.g.: Circuit Architecture and FPGA Implementation Advanced VHDL Implementation Sigmoid Function and Exercises A VHDL basics tutorial is not the scope of this channel. I regret.
@ostrov11
@ostrov11 8 ай бұрын
спасибо, хорошая работа
@Suraj-uk9wu
@Suraj-uk9wu 8 ай бұрын
Very helpful video sir .
@qamarrasheed8710
@qamarrasheed8710 9 ай бұрын
Hi Sir, I am working on image processing using de 10 fpga. The code provided in the description and comments section is not working. Kindly update it or share via google drive if possible. Thanks
@marcowinzker3682
@marcowinzker3682 9 ай бұрын
Hello, there are several DE10 boards and they are really different: Standard, Lite, Nano The design is for DE10-Standard.
@MohamedMostafa-tn3qo
@MohamedMostafa-tn3qo 9 ай бұрын
hello sir im just asking can i compile a c code into fpga ??
@marcowinzker3682
@marcowinzker3682 9 ай бұрын
No. In theory there are tools for that, but they have limitations and you need to have good knowledge of the design flow.
@MohamedMostafa-tn3qo
@MohamedMostafa-tn3qo 9 ай бұрын
@@marcowinzker3682 I'm sorry to bother you sir but II have a graduation project to make a robot car (self driving car that do lane detection and object detection ) using FPGA . I Made it with raspberry pi but it seems little bit confusing with FPGA that's first time for me to deal with it and VHDL ( even i dont know all basics of VHDL) . do you have suggestions or where should i start or something ?? thanks in advance
@marcowinzker3682
@marcowinzker3682 9 ай бұрын
@@MohamedMostafa-tn3qoYes, for your project you need to understand the fundamentals of FPGAs and VHDL.Tthere are several options, but I can not give a recommendation. I regret.
@MohamedMostafa-tn3qo
@MohamedMostafa-tn3qo 9 ай бұрын
@@marcowinzker3682 thank you❤️
@MohamedMostafa-tn3qo
@MohamedMostafa-tn3qo 9 ай бұрын
i just understand why you regret you r channel is a real treasure <3 thanksss @@marcowinzker3682
@muhammedalikaya268
@muhammedalikaya268 9 ай бұрын
thanks sir, can the code be assigned to the xilinx FPGA board?
@marcowinzker3682
@marcowinzker3682 9 ай бұрын
Yes, but you need to do certain adaptations, for example the ROM for the block-memories.
@muhammedalikaya268
@muhammedalikaya268 9 ай бұрын
sir how to find these adaptations that need changes and how can i do the adaptations, i used digilent genesys 2 FPGA board, thanks your return.
@marcowinzker3682
@marcowinzker3682 9 ай бұрын
@@muhammedalikaya268Best approach: Try to compile the code and the software will give you error messages for elements to be adapted.
@2011HPS
@2011HPS 9 ай бұрын
Hi prof. Why do we approximate to the nearest power of 2
@marcowinzker3682
@marcowinzker3682 9 ай бұрын
Because the hardware implementation of multiplying by a power of 2 requires no circuit elements. It is just a different connection of the signal bus. For example, for a multiplication by 8 you shift the wiring of the signal bus by 3 bit, as the factor 8 is 2^3.
@KristianDjukic
@KristianDjukic 9 ай бұрын
very interesting and thanks for publishing this stuff
@rezayazdani2918
@rezayazdani2918 11 ай бұрын
thank you for your useful video.
@sareefsarraj7665
@sareefsarraj7665 Жыл бұрын
Prof, It works fine with questa, but if we want to run on vivado, it did not work when run as it is, is there any changes to do or any ways to produce bitstream as our aim is to run on fpga
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
I have used several FPGA design flows in the past, and Xilinx is high quality provider. But of course there are small differences in interpretation of VHDL code. I did not check this design with Vivado. My suggestion to you: Please check all warnings of the compilation. Often there are hints. You can also compare the results of Questa and Vivado. How many FPGA elements do they use? How many for each submodule? If there are huge differences, part of that code is interpreted differently.
@kejiangguo
@kejiangguo 9 ай бұрын
Prof, I run it on vivado successfully~@@marcowinzker3682
@abuali5513
@abuali5513 Жыл бұрын
Have you deployed in fpga board? Is it safely feasible to transfer the whole model to fpga? Thanks professor
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
We have not done that. The design flow showed that the methodology is feasible, but we found it (at the time of production of the video) not yet mature enough for deployment on an FPGA board.
@abuali5513
@abuali5513 Жыл бұрын
Is it possible to have this done by hls4ml without dealing directly with VHDL. Thank you professor for the great videos
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
Evaluation of HLS4ML has been done by a student in a project. I have not been following development of HLS4ML, so I can't give a good estimate on the effort to implement the algorithm with that tool.
@bidyutbikashborah800
@bidyutbikashborah800 Жыл бұрын
Hello Prof., i would like to start working with DNN in FPGA, can you suggest me good latest board.
@akashreddyshetty1980
@akashreddyshetty1980 Жыл бұрын
does this project works on spartan 6 sir
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
Yes, but you need a board with video input and video output. It is much easier to use our free remote-lab.
@BhukyaRajkumar-wx6xq
@BhukyaRajkumar-wx6xq 10 ай бұрын
How to give video input to the FPGA board sir? Do we have to modify the code for giving video input
@marcowinzker3682
@marcowinzker3682 10 ай бұрын
@@BhukyaRajkumar-wx6xq The code has a video input. This is the red, green, blue 8bit input plus 4 control signals: hs, vs, de, clk.
@BhukyaRajkumar-wx6xq
@BhukyaRajkumar-wx6xq 10 ай бұрын
@@marcowinzker3682 sir can I contact you I have some doubts regarding implementing this project. I would like to contact you in your free time
@hanskloss8804
@hanskloss8804 Жыл бұрын
Hi, could you please recommend any books for real time image processing in VHDL for beginners?
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
I recommend "Digital Signal Processing with Field Programmable Gate Arrays" from Uwe Meyer-Baese.
@mac8544
@mac8544 Жыл бұрын
​@marcowinzker3682 Many Thanks!
@devansh5562
@devansh5562 Жыл бұрын
Any specific reason for using matlab/octave and Quartus instead of Vivado?
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
We are using Intel FPGAs in our lab. Other FPGA providers are also offering good products.
@thienphu2952
@thienphu2952 Жыл бұрын
amazing professor
@Ajithkumar-r2v
@Ajithkumar-r2v Жыл бұрын
pls send the source code
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
Links to source code are available.
@firedrive45
@firedrive45 Жыл бұрын
​ @marcowinzker3682 Hi Mr.Winzker, I am developing the implementation of image correction on camera feed and wanted to know what kind of FPGA approach would be adequate for changing the addresses (positions within the images) of pixels. Each pixel has an initial address and each pixel has a final address at which they should be displayed instead. Please let me know and thanks for the great videos. This is done at 30Hz with 1920x1080 resolution. Is such a thing even possible?
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
For this task you need a large memory. The on-chip memory of an FPGA is not suited, so you need an external memory like SRAM or DRAM. Then you have to calculate the data rate for accessing the memory. You find an example in the following paper: M. Winzker; P. Pirsch; J. Reimers, "Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs," IEEE ISCAS 1995.
@ChizkiyahuOhayon
@ChizkiyahuOhayon Жыл бұрын
Your lecture is crucial to me because it's exactly what I have been doing! I have been studied SNNs for several months but I don't know much about FPGA. Can you tell me which kind of FPGA I need to buy in order to perform tasks in machine learning especially SNNs? Thanks for your wonderful lectures.
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
This is a difficult question, a little bit like "Which car shall I buy?" Basically, you need to consider two things: 1) FPGA-capacity and 2) Interfaces FPGA-capacity depends on the size of the NN you want to implement. FPGAs are pwoerful, so for a start with small/medium experiments, a regular FPGA is sufficient. Interfaces are important to get your data in and out. The lecture describes video processing, so it needs video in and video out. If you do audio processing you need these interfaces. Or maybe you want to use an embedded-CPU, then you need a corresponding FPGA. Often the FPGA-boards provided for educational purposes are a good choice. Terasic offers Intel-boards, Digilent has Xilinx-boards.
@ChizkiyahuOhayon
@ChizkiyahuOhayon Жыл бұрын
@@marcowinzker3682 Thanks very much for your detailed reply! It was inspiring and motivating! You are such a generous, dedicated and knowledgeable teacher!
@arunuday6109
@arunuday6109 Жыл бұрын
Awesome ! Thanks for publishing this.
@mbuaesenju8514
@mbuaesenju8514 Жыл бұрын
thank you. Perfect!
@frederikvanaverbeke8840
@frederikvanaverbeke8840 Жыл бұрын
These are great videos! I am really learning something. One Q about this specific one though... how should I understand your label file? You draw a box around the roadsign and black out everything outside, with which you tell the net that every pixel in the box is yellow, even if there are different shades of it. Then the R & G & B values of every pixel in the original file are used as training data. So, if everything goes well, the neural net, once trained, can tell for every set of RG&B values if it is a shade of yellow. Yet, in the label data, there is a black arrow and some black characters, which you label as a shade of yellow since they are in the box you draw. Yet, when applied to the image, the neural net indeed designates the pixels in the arrow as non-yellow. Did it manage to do that because it also learned from the regions outside the box? So, does that mean that the labeling of the pixels (your box) does not have to be perfect? Am I getting this all right?
@marcowinzker3682
@marcowinzker3682 Жыл бұрын
This is a good observation! You can see it from three perspectives: 1) If you want to detect yellow color, you should make the mask only for the yellow area, so not for the black arrow and character. 2) If you want to detect the sign, you can argue, that the black arrow and character belong to the sign. But black is ambiguous and can belong to the sign and the background. Therefore it is not detected as a sign. My approach is: 3) I use training data that is not perfect. There are the black areas and also at the edge of the sign, I was a bit lazy. In this application, the result is OK and the NN detects yellow. With better data, maybe better detection is possible.
@aratishah3691
@aratishah3691 Жыл бұрын
Thank you, Professor.
@JustinCao52
@JustinCao52 Жыл бұрын
Prof, thank you for putting up these work. Your channel is golden!