Process Corner Analysis of 7T SRAM in Cadence Virtuoso
6:05
Process Corner Analysis of 7T SRAM in Cadence Virtuoso
Ай бұрын
Design of SRAM 7T Cell in Cadence Virtuoso and SNM Plot #cadence #virtuoso #SRAM
5:27
Design of SRAM 7T Cell in Cadence Virtuoso and SNM Plot #cadence #virtuoso #SRAM
Ай бұрын
NAND Gate Layout in Cadence Virtuoso
8:18
NAND Gate Layout in Cadence Virtuoso
2 ай бұрын
Design of SRAM 6T Cell using stacking effect in Cadence Virtuoso
6:49
Design of SRAM 6T Cell using stacking effect in Cadence Virtuoso
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Design of 3 input AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
9:34
Design of 3 input AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
3 ай бұрын
CMOS Inverter Layout Design using Cadence Virtuoso | DRC Check
17:59
CMOS Inverter Layout Design using Cadence Virtuoso | DRC Check
3 ай бұрын
NMOS Id vs Vgs Characteristic using Cadence Virtuoso | Power Consumption
5:00
NMOS Id vs Vgs Characteristic using Cadence Virtuoso | Power Consumption
4 ай бұрын
NMOS Id vs Vds Characteristics using Cadence Virtuoso
6:15
NMOS Id vs Vds Characteristics using Cadence Virtuoso
4 ай бұрын
DC Analysis and Power Dissipation of SRAM 6T Cell in Cadence Virtuoso
3:35
DC Analysis and Power Dissipation of SRAM 6T Cell in Cadence Virtuoso
4 ай бұрын
Design of SRAM 6T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
11:39
Design of SRAM 6T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
4 ай бұрын
Design of Half Adder Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
4:43
Design of Half Adder Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
5 ай бұрын
Symbol Creation of XOR Gate in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign #virtuoso
4:19
Symbol Creation of XOR Gate in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign #virtuoso
5 ай бұрын
Design of XOR Gate Schematic in Cadence Virtuoso
9:05
Design of XOR Gate Schematic in Cadence Virtuoso
5 ай бұрын
Design of 2×1 Multiplexer using transmission gate logic in Cadence Virtuoso #cadence #virtuoso #vlsi
13:42
Design of 2×1 Multiplexer using transmission gate logic in Cadence Virtuoso #cadence #virtuoso #vlsi
6 ай бұрын
Design of NOR Gate Schematic in Cadence Virtuoso #virtuoso #cadence #vlsi #vlsidesign
7:59
Design of NOR Gate Schematic in Cadence Virtuoso #virtuoso #cadence #vlsi #vlsidesign
7 ай бұрын
Design of OR Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
7:28
Design of OR Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
7 ай бұрын
Design of NAND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
8:24
Design of NAND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
7 ай бұрын
Design of AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
11:01
Design of AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
7 ай бұрын
Inverter using Stimuli #cadence #virtuoso #vlsi #vlsidesign
5:53
Inverter using Stimuli #cadence #virtuoso #vlsi #vlsidesign
7 ай бұрын
Inverter design in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
16:31
Inverter design in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
8 ай бұрын
Пікірлер
@NandeeshVerma1
@NandeeshVerma1 7 күн бұрын
Hello Ma'm Can u post a complete video tutorial of how to do the simulation of read and write operation and timing of this 6t sram cell and in cadence virtuoso and how to find out rsnm, wsnm, hsnm etc?
@a_42_kunaldhangun3
@a_42_kunaldhangun3 9 күн бұрын
In input 0,0 the output is showing 1 which is wrong
@dinhhoang-o1i
@dinhhoang-o1i 11 күн бұрын
why did you add VDC=1v at point Q.when BL line is already powered.i really need explanation
@dinhhoang-o1i
@dinhhoang-o1i 11 күн бұрын
why did you add VDC=1v at point Q.when BL line is already powered.i really need explanation
@AbhimanyuSharma-e6q
@AbhimanyuSharma-e6q 11 күн бұрын
Thank you very much mam🥰🥰🥰🥰🥰🥰 please teach about vlsi concepts of mosfets and help us to design some digital circuits
@kusumapasupuleti7496
@kusumapasupuleti7496 16 күн бұрын
Can u upload 10t sram transient analysis
@LaLa-x3y
@LaLa-x3y 28 күн бұрын
Can i calculate the SNM after getting the butterfly curves, ma'am? Thank you
@hainguyenthanh8375
@hainguyenthanh8375 Ай бұрын
I looking forward to video related Ip, memory, such as: DDRAM, DDRAM1,2,3,... 🤗
@mr.vardhan8632
@mr.vardhan8632 Ай бұрын
Please upload video on 12t sram
@ch.yaminic1361
@ch.yaminic1361 Ай бұрын
Maam please do a video on 12 t sram
@CHINTADAMADHUSUDHANARAO
@CHINTADAMADHUSUDHANARAO Ай бұрын
Maam please do a video on 12t sram
@Sunny_9048
@Sunny_9048 Ай бұрын
Mam can you explain Design of low power SRAM using 10Transiator
@CadenceVLSI
@CadenceVLSI Ай бұрын
kzbin.info/www/bejne/nWHJe52Yn8SCpKc
@Sunny_9048
@Sunny_9048 Ай бұрын
Mam is cadence software Is free
@CadenceVLSI
@CadenceVLSI Ай бұрын
No
@hainguyenthanh8375
@hainguyenthanh8375 Ай бұрын
How to identify technology 90nm and 180nm Using cadance ?
@CadenceVLSI
@CadenceVLSI Ай бұрын
When you started making the library, you must have chosen the technology you wanted to use. And incase you want to check the technology later, follow these steps: 1. Go to 'Tools → Library Manager' in Virtuoso. 2. Find the library you're working with, right-click on it, and select 'Properties.' 3. You'll see the Technology Library name, which indicates the technology node (e.g., 90nm or 180nm).
@hainguyenthanh8375
@hainguyenthanh8375 Ай бұрын
@@CadenceVLSI thanks your answer
@kajalkhairnar809
@kajalkhairnar809 Ай бұрын
Keep it up👍🏻
@SANJAYYADAV-jp2dt
@SANJAYYADAV-jp2dt Ай бұрын
good
@ShubhamYadav-zj4st
@ShubhamYadav-zj4st Ай бұрын
Good going 👍
@whathehellooo
@whathehellooo Ай бұрын
can u do 10T SRAM (TRIO)
@CadenceVLSI
@CadenceVLSI Ай бұрын
kzbin.info/www/bejne/nWHJe52Yn8SCpKc
@vinayakulkarni5336
@vinayakulkarni5336 Ай бұрын
Thank you so much mam for this video 😊
@SANJAYYADAV-jp2dt
@SANJAYYADAV-jp2dt Ай бұрын
Simplyfied and understandable
@karanchoudhary5652
@karanchoudhary5652 Ай бұрын
Why their is a spike in the output waveform
@CadenceVLSI
@CadenceVLSI Ай бұрын
When both the inputs are 1 we generally see these spikes, this happens when the inputs are not perfectly synchronised and when there is a slight delay in one input.
@vinayakulkarni5336
@vinayakulkarni5336 2 ай бұрын
mam iska 7T SRAM CELL ka video mil sakta hai kya ?
@CadenceVLSI
@CadenceVLSI Ай бұрын
kzbin.info/www/bejne/emLXcn-gZ9J2aM0
@user-lt7wt3ku1d
@user-lt7wt3ku1d 2 ай бұрын
Well explained ma'am Thankyou
@the.businesspreneur
@the.businesspreneur 3 ай бұрын
Pls make a vdeo on its layout too...
@CadenceVLSI
@CadenceVLSI Ай бұрын
watch this for basic kzbin.info/www/bejne/lYmaYWRsnNl0fNU
@mrahil1333
@mrahil1333 3 ай бұрын
Hi this layout is not good poly cannot be bent
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
It's not that you can't bend it-you can. However, you need to ensure it doesn't overlap with other poly. This is just an explanation for designing the layout; if you can create a more accurate design, that would be even better.
@RoshanKumar-vf4tt
@RoshanKumar-vf4tt 3 ай бұрын
Mam can you make video on 3 input AND gate?
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
kzbin.info/www/bejne/l3zGn6yBjcmietE
@pratikmohanty1498
@pratikmohanty1498 3 ай бұрын
How you designed the invertersymbol???
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
I've already designed that in my previous video kzbin.info/www/bejne/pXSkpqZqdpamick
@tamphuc6159
@tamphuc6159 3 ай бұрын
Please give me the link to download cadence virtuoso
@flyingcolor1420
@flyingcolor1420 3 ай бұрын
Tq sm mam, please keep doing videos, honesty I am requesting you 🙏
@verma8308
@verma8308 4 ай бұрын
Thanku so much ma'am.good explanation
@inderjitsaini9303
@inderjitsaini9303 4 ай бұрын
Thank you for the video, I was trying this today. Just to confirm, the butterfly curve in the video is for the READ Mode of the 6T SRAM Cell right?
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
The butterfly curve in SRAM 6T is basically used for evaluating and ensuring the stability and robustness of the memory cell.
@elijahmikaelson8027
@elijahmikaelson8027 4 ай бұрын
Could you also make it's layout with DRC LVS ERC and post layout simulations.
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
kzbin.info/www/bejne/lYmaYWRsnNl0fNU
@hritammitra7836
@hritammitra7836 4 ай бұрын
Mam how to install cadence virtuoso in my system (crack or non-licence version)? Is it possible?
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
Yes, it can be done, and I'll try to upload a video showing how to install it.
@user-lt7wt3ku1d
@user-lt7wt3ku1d 4 ай бұрын
👍 helpful
@smeetchandra3762
@smeetchandra3762 4 ай бұрын
Nice trick mam in my software ,other methods are not working but suddenly I tap your video and boom 💥 your trick works for my software , thanks 🙏
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
Thank You!
@user-lt7wt3ku1d
@user-lt7wt3ku1d 4 ай бұрын
Well understood. Thankyou for your efforts ma'am
@user-lt7wt3ku1d
@user-lt7wt3ku1d 4 ай бұрын
Excellent explanation ma'am
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
Thanks a lot.
@joelmatthew1826
@joelmatthew1826 4 ай бұрын
Inverter must be 2 inputs yes?
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
No, an inverter has only one input. It is a basic digital logic gate that outputs the opposite value of its single input.
@BrindhaThanjavur
@BrindhaThanjavur 7 ай бұрын
Can you pls help me in debugging DRC errors??
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
Sure, if you’re still having issues, let me know in the comments.
@BrindhaThanjavur
@BrindhaThanjavur 3 ай бұрын
I am getting psubstrate stamp error mult and psubstrate stamp error connect. I can't rectify these errors.
@abhisheksharma2065
@abhisheksharma2065 7 ай бұрын
Iska layout ka video banaye na in layout XL Launch me
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
Sure, I will
@Ravikumar-zh2cp
@Ravikumar-zh2cp 7 ай бұрын
Please make video on sram cell design video
@CadenceVLSI
@CadenceVLSI Ай бұрын
watch this kzbin.info/www/bejne/pZDEY36CqJV0odEsi=amSSu62RNm2pBtD2
@user-lt7wt3ku1d
@user-lt7wt3ku1d 7 ай бұрын
Great explanation. Thankyou very useful 🎉
@CadenceVLSI
@CadenceVLSI 3 ай бұрын
Thank You!