In system synchronous clocking, all components in a system are clocked by a single global clock source. The clock signal is distributed throughout the system, and all the components operate in sync with this global clock.In source synchronous clocking, the clock signal is transmitted along with the data from the same source. The receiving device uses the transmitted clock to latch the incoming data, ensuring synchronization between data and clock at the destination.

we can use a T flip-flop operating at posedge or negedge( I am taking posedge) . Now give the input T=1 at posedge and for the next posedge also give T=1. Now the T-on of the output is the time period(T) of the clock, we know that f=1/T. Is it correct?

You have used both blocking and non blocking assignments in the same always block. Won't it create any issues?

good content in present scenario

divide by 3 circuit

Very nice. Great initiative sir 🙏 Nicely organized ...

Good explaination

Bifurcation

Just Perfect

8 bit ring counter

We can use a T flip flop input of which is a signal which gets high when address is 7 and output of this flip flop is our desired output.

When we give f/4 to a -ve edge triggered DFF, it just delays the signal, but the frequency of the signal doesn't change. When you check the clock diagram for both the outputs after ORing them, we see that we will get 2.5 clock cycles of logic 1, but also we will only have 1.5 clock cycles of logic 0. Hence, i feel that we did not get f/5, but we have f/4 with 3.5 clock cycles of logic. If i am wrong, please correct me. Thank you And please confirm if I am right or wrong

Then what does the synthesis take into consideration while building a circuit? However we write the always block, we are getting the same result.

Can we also do another thing: If we take another output counter whose outputs are Q2', Q1' and Q0'. But instead of giving the clk directly to this counter, we need to give clock with half frequency. Then automatically, the output of this counter is halved. In the input counter, we see that the output Q0 has half the frequency of the clk. Freq of Q0 = fclk/2. Freq of Q1 = fclk/4. Freq of Q2 = fclk/8. Hence for our output counter, if we give Q0 as the clock, we can also achieve the slow counter. Is this approach also, correct? Open to suggestions.

In generic case, shouldn't it be (ip=='hi) ??

I have a doubt. At 2.03 you said at negative edge, 2nd F/F starts transmitting the data, but that is the case when the F/F is negative edge triggered f/f , here it is still positive edge triggered . it's just that the applied clk signal is inverted. Please correct me if i am wrong

Can we write assign aff[0] = a; intead of always aff[0]=a;

(at 5:23 ) say , after fabrication of chip, which violation can be resolved? setup violation can be resolved by increasing the frequency of operation? and what abt hold violation?

VHDL? Nah Verilog? Nah System Verilog!!!!!

Sir could you please make a thorough series on Reset Recovery and Removal Concept, Reset Domain Crossing Issues, and Techniques to Solve The Reset Domain Crossing issues? I see bunch of videos on youtube, but they lack the touch of you. (Basically they are crap in my view to be honest) Anyways, I am eagerly waiting for that series of videos from you. Thanks! :)

Setup and Hold time of Latch itself (another video you did) and this one on top of that video, made me confused :D How does the setup and hold time of the individual latches are incorporated into the equation of the setup and hold time of the FFs? :)

Very very infomative

Shouldn't it be mentioned that, the output of the reset synchronizer is fed to the downstream flops' reset input, but it is assumed that those flops are in the same clock domain as the reset synchronizer? Otherwise, you could still experience metastability downstream.

Calling it Minimum Pulse Width Requirement is confusing. My mind is going to the required input pulse width. It took me long time to understand you were talking about the duration of TON in a clock period when you referred to it as Pulse Width.

pls don't make us force to pay sir we are learners to seek knowledge if the video is in playlist in youtube then why blocking the content only for membership users only this is not fair sir so our knowledge is now incomplete and you also don't get the satisfaction of teaching to students, am I right sir if member ship is must means put it as course sir not in youtube.

Adding 1ns delay on the clock path to the second flop (the flop in the middle) would be the easiest way to fix this without a functional eco as suggested in this video

Detailed explanation 😊

Hello sir, when you are combining edge detector and pulse stretcher to generate 3 clock cycles pulse; there edge detector won't generate single pulse; it will detect multiple edges if there are multiple posedges . So, this approach may not work.

is this code synthesizable ?

Please sir make videos on Asynchronous FIFO DESIGN

Nice sir❤❤❤❤

excellent

Very nice information. In this we can increase no. Of bits of the registers from 8 bit to atleast 64bit or more to capture more data

module (in, clk, reset,out); input in,clk, reset; logic [9:0] count; output logic out; logic out_reg; assign out_reg = (count >10’d511)?in:out; //registering to avoid combinatorial loop always_ff@(posedge clk) begin if (! reset) out <= 1’b0; else out <= out_reg; end always_ff@(posedge clk) begin if (! reset) count <= 10’b0; else count <= count + 10’b1; end end module

Where are the other videos of this series????

What is the solution for this? I could not find proper solution for freq doubler circuit (if we first use mod-3 and then freq doubler post that). What could be the proper synthesizable way to do it.

New ff with ip - Q1 and clock to negative edge and its output Q_FF For Duty 10% = Q1 AND ~Q_FF Right??

This video is a gem, I have tried to understand this from various resources, but this video gives me a fundamental understanding. Thank you for making this video, looking forward to learning something about Zebu EMULATOR, as it becomes widespread in interviews.