Waiting for part 2 anish dada !!

Waiting for part 2

bhaiya notes pdf v dedo plz

bhaiya part 2 v jaldi dedo

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Bhai pls part 2 bhi jldi lana is sem me coa h and i believe this is going to be one of best lecture in utube

Eagerly waiting for part 2

Thanks dada

i am waiting for part 2

Kudos to you sir👏

Thank you, hoping for part-2 also.

Thanks bro

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Bro, I am 2024 ECE passout , I have interest in Embedded system and VLSI. To get a job we have to join coaching centre or not .is coaching centre is necessary to get a job.Please reply

super bhaiya ❤

Thanks Brother ❤

Thanks ❤

Huge respect for you Anish Bhaiya ❤❤

Thanks Bhaiya ❤❤

Thanks Sir 👍😀 Regarding the mismatch problem in this circuit, how can I explain its operating principle and complete the actual circuit design and layout on this tapout ic?🤔🤔 Teach me ❤

Would love more such questions sir

bhaiyaa kuchh help kaar dijiyeee vlsi industry maii enter hoone kee liyaaa...

Thanks again Anish sir 🙌🏻

Can anyone guess what happens to the output if the opamp is ideal in all aspects. Do you think that the charge sharing(between the caps) happens when S1 is closed?

Bhaiya plz tell the roadmap for embedded system...i am very confused

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RC charge vc(t) =vo(t) =vi*(Ao/1+BAo) *(1-e-t/(RoC/1+BAo))u(t) 🤔 And then discuss with Slew rate 🤔

When S1 is on the charge sharing happens instantly due to the ideal switch but then after that the combined capacitance of 101nF should still be charged to 10/11Vin instead of 100/101 * 10/11 * Vin finally since the RC time constant is still pretty much the same. Please correct me if I am wrong.

Thank you Sir 👍 Very good sessions! RC<<T and then vo(t) exponential charge wavefrom is rising slowly and the steady state is close to vi=1v So vo(av)={0(T/2-0)+(T-T/2)*(100/1+BA)*(10/1+BA)}/T={(100/101)*(10/11)*T/2}/T=0.45 v Ps:B=1 🤔

in homework problem (G) : Before switch is closed all three caps will have -1v across them and after switch is closed then also -1v across all of them . hence Vx=-1v before and after switch is closed. Am i correct ?

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It is very interesting circuit!😁 Thank you @@

hi it would be wonderful if you can tell me what should be the roadmap for VLSI PS:how to start with analog electronics for VLSI

Hi , is there good scope for ATE test engineers in Semiconductor industry?

Great content sir!! I am currently doing my 4th year from tier 3 clg . What is your opinion on getting into some training institute like Veda iit for career in vlsi field. Please do reply!

What videos would you recomend we watch for the analog electronics portion from the playlist?

In ques 3, If there is no negative feedback in the opamp then how did we assume its both terminals voltages equal?

Very clear explanation, very interesting circuit！Thank you 😁 1,3,4 for me is Not hard!

Bro I am a software engineer, I am interested in Semi conductors, should I switch?

konse projects karne chahyiye

Detailed video... Very good inputs... Thanks for the inspiration....

one of the best question on plotting output waveform, totall master question mixed of RC circuit concept and mosfet , pass transistor logic. so nice anish, lots of respect to you

Please mention her linkedln id, if possible.

thank you

very informative thank you

Hi Everyone, If you have any particular questions you can contact Suchismita Di here - topmate.io/suchismita_bose For Comprehensive Courses you can visit - prepfusion.in/new-courses?examId=7

Thank you so much brother 😊

32:22 We have three capacitors in parallel, they all will settle to a final voltage Vx=-V (this is instantaneous). Turning the switch on/off doesn't have any effect as we are connecting the ground to itself. My question is, At what time the initial conditions are defined for this circuit? Once the circuit is formed and the capacitors are made to be in parallel, we can't define two different initial voltages for them. So, we must have a two more switches to define initial conditions isn't it?

10:21 Hi Anish, the point that you are making here in Case 2 situation - "the extra current flows through the source" is not valid here. We started our discussion with a point that the n side slope is smaller than p side in Case 2, which makes the dione ON. Once the diode is on, the current cannot flow into n side of the diode (into the V source). For Case 2 situation: 1. The diode(ideal) cannot have any current in the reverse direction. 2. A voltage source when connected to a lower potential than it's terminal voltage will always deliver power. Hope you correct the statement :).

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