Hardware Modeling Using Verilog

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@toheedh 13 күн бұрын

At 26:35, d_out and t should've been declared as reg variable since they are placed on the left side in an always blocks. showing that this is a behavioral simulation.

@ELECTROPHILLIC 19 күн бұрын

27:43 ( Branch Operation ) : if the cond == 0 only then send the ALUOUT to PC else if cond ==1 send NPC value to PC .

@stecklerdav 28 күн бұрын

a genius thanks

@techmad8204 Ай бұрын

how are writing to a register when we're reading it? like there is no logic in assign statement to dtop this is it fine?

@user-bp4vs2kz2y Ай бұрын

sir which simulation tool it is?

@bhuvanverma7223 Ай бұрын

is this ppt which used in all the vedios is available?

@Gateprep2024 2 ай бұрын

sIR i am using icarus verilog and getting the output i am getting R1 - 10 R2 - 20 R3 - 25 R4 - 4 R5 - 29 can somebody send the code

@shalinidey1896 2 ай бұрын

Detailed yet crisp lecture series covering such broad spectrum. Thank you sir for the valuable course. Hope more such will follow!

@paradox2738 2 ай бұрын

once in state 5 and the q0,q1 is 11 it will not leave state 5 because in the second always block we are looking out for state change and we not change out of state 5

@suvirnupadhyay8696 2 ай бұрын

at 29:57 , there is a mistake .....if zero is applied how can it make transition to two different states with applied input is same.

@shashwattripathi5872 3 ай бұрын

in last module "simple_latch", shouldn't 't' be of type 'reg' as it has been assigned inside 'always'?

@NPALEPUNITHINSANTOSHKUMAR 3 ай бұрын

In IF why we use pc+1

@srikanthvadithya9522 3 ай бұрын

Program counter is the special type of register which holds the address of next instruction to be executed.. So whenever we write pc << pc+1 Instruction fetch(IF) has also same functionality as mentioned in lecture

@ELECTROPHILLIC 19 күн бұрын

@@srikanthvadithya9522 Actually PC will have the current address of the RAM location , but NPC will always have the next address of RAM and that value is loaded to PC .

@SrikarVarma-jw8hh 3 ай бұрын

in 18:49, explicit association should be "<.> <ports_from_module>(<ports_from_testbench>)", anyone can notice and reply please

@shayokrahmanemon731 Ай бұрын

yes I also notice this and i think you write the correct one

@arghya.7098 3 ай бұрын

15:07 can't we achieve the same functionality using blocking assignment?

@arghya.7098 3 ай бұрын

3:53 isn't 1^x = x' (x complement)?

@NikhilMandoli 3 ай бұрын

no.. 1 ^ X= X

@honeygarg2946 13 күн бұрын

yes it should be x'

@arghya.7098 13 күн бұрын

@@honeygarg2946 I think prof is correct. As, x is a state of variable, not a Boolean variable itself.

@Tanaypasumarthi 3 ай бұрын

6:34 In non blocking condition what will be the result when time delays are different

@arghya.7098 3 ай бұрын

all the data assignment will take place after their respective time delay. for example, x <= #5 (a | b); y <= #7 (c & d); then assignment to x will take place at t = 5, and assignment to y will take place at t = 7 for blocking assignment, i.e., x = #5 (a | b); y = #7 (c & d); here, assignment to x will take place at t = 5, and assignment to y will take place at t = 12

@Awakened_Pot 3 ай бұрын

Thank you for this amazing series Sir❤

@Tanaypasumarthi 3 ай бұрын

9:26 count has to be intialised to zero right??

@sakshisingh4197 3 ай бұрын

Reset is there for that

@sakshisingh4197 3 ай бұрын

In testbench you can start reset before clk so it will initially go to 0

@saiteja3717 3 ай бұрын

in time 10:20 state diagram redundant states are there sir

@mdfaizan1887 3 ай бұрын

Thankyou sir !!!

@TharunMalla 3 ай бұрын

where we can download the notes??

@sanketnaik387 3 ай бұрын

I guess for the modified method, in last part you forgot to write next state =S1 and S2 in that 2nd always block

@HarshaVardhan-c9s 2 ай бұрын

did you implement that? its not working for me

@tee-nw5vx 3 ай бұрын

where can i get this ppt

@srijandwivedi294 4 ай бұрын

17:00

@srijandwivedi294 4 ай бұрын

28:00

@nityamaheshwari8259 4 ай бұрын

in full adder circuit there is no 3 xor circuit present and some verilog code is not correct , please make new playlist

@yogeshyadav9023 4 ай бұрын

Read last comment of this post , and try to understand, u will get your answer that ,this full adder ckt is also correct

@pawansharma6226 4 ай бұрын

use delay #1 before display, soo that the input and output are settled before display. Now you will get correct Output.

@nikhilteja7018 4 ай бұрын

14:40 Why did we use mux16 to1 M' instead of 'mux16to1 DUT'

@Gate_IITB 11 күн бұрын

We can give any name to a module that is called( instantiated), therefore, we can use both DUT or M anything that goes good to you

@prabhatsati4387 4 ай бұрын

why is there a latch at the last stage , we can directly transfer the output, is it the necessity of code or necessity of the question??

@avinasha237 4 ай бұрын

Always is checking posedge or negedge of clock. But clock generation code is not written. clk1 =~clk1 clk2 = ~clk2

@arghya.7098 3 ай бұрын

ig the testbench program takes care of clk generation. correct me if i'm wrong.

@avinasha237 3 ай бұрын

@@arghya.7098 it's right... Thank you

@avinasha237 4 ай бұрын

Why need temporary variable for both a and b . A single temporary variable is enough to swap. a = 8 ; b =5; temp = a; a = b; b = temp; output: a = 5 ; b = 8

@sakshisingh4197 3 ай бұрын

this is also fine.you can do it with single variable also

@avinasha237 3 ай бұрын

@@sakshisingh4197 how?? Is that what you mean by using non blocking assignments?

@phaneendrakumar658 4 ай бұрын

Here I think we cannot instantiate any modules/UDP inside a UDP. But how did you instantiate TFF UDP inside the ripple_counter UDP at 26:32 ( which is a UDP)??

@Random.PCB. 6 ай бұрын

Very clear, thank you for your service 🫡

@nenavathharisingh3231 6 ай бұрын

Isn't that decoder a dmux ??

@arghya.7098 3 ай бұрын

i guess he mistakenly told demux and decoder as same thing

@princessipsi9433 7 ай бұрын

It's Verilog or system Verilog

@maradanitejaswi1201 3 ай бұрын

Verilog

@arghya.7098 3 ай бұрын

he mentioned it is verilog, at the beginning of the course

@loknathd860 8 ай бұрын

31:50 at examles the parameter up=2'b00 and so on...i think it could be like this.

@peekaykarekar7865 8 ай бұрын

In the MUX Module, why is the sel not 4 bits?

@shubhayansarkhel4363 8 ай бұрын

in palnitkar it is written that multidimensional arrays are not permitted in verilog, integer matrix[7:0][15:0] this is an illelgal declaration in verilog. which one to follow sir's or book?

@mdfaizan1887 4 ай бұрын

they are not supported in verilog but in system verilog they can be used

@Mohamed_Shabaik 8 ай бұрын

man this is so hard

@gabsingh100 6 ай бұрын

That's what she said

@Mohamed_Shabaik 2 ай бұрын

Classic Michael Scott moment 💀

@souhardhyapaul1158 9 ай бұрын

At 13:00, third line, S=1 is wrong, it should be S=0.

@arghya.7098 3 ай бұрын

yeah, i've been thinking the same

@anveshpandey9817 Ай бұрын

Corrected later in the vid

@dhrubajyotimandal 9 ай бұрын

why do we have built in primitives? while we can already implement things behaviorally like "assign x=a|b;" instead of "or (x,a,b);"? does those primitives serve some different purpose?

@sanjeevyadav-lw4ky 9 ай бұрын

at 20.34 , clr =1 is applied after 7 (2+5), not at the edge of clk

@Deepak_3860 9 ай бұрын

*To download pdf notes* *1* Type hardware modelling using verilog indranil sengupta notes . *2* go to assignments (see at bottom) & download it as zip.

@rashikabobade4769 3 ай бұрын

@Deepak_3860 where to type

@durgeshydv3829 2 ай бұрын

from where we have type for download the notes

@AchuthaAswinNaick Ай бұрын

@@durgeshydv3829 google

@iiitk_nani Ай бұрын

@@durgeshydv3829 google

@ranjanyadav9011 10 ай бұрын

But sir how can at 26:48 the t be modelled as a latch as it is defined as a net data type and you said that net data types can only be modelled as wire??

@guhanrajasekar5993 9 ай бұрын

I think there is a mistake there. I think ' t ' should have been declared as a variable of type ' reg ' .

@DIVITSHARMA-nj9hn 4 ай бұрын

@@guhanrajasekar5993 yes i also feel the same , but it is interesting that no one noticed in 6 yrs!!😲😲

@sakshisingh4197 3 ай бұрын

Oo i noticed after reading this ...that should be reg.

@maradanitejaswi1201 2 ай бұрын

@@sakshisingh4197 Can you explain d_out can't be reg? As it is used on the left side ryt? I believe both t and d_out should be declared as reg.

@dileepnaidu3850 10 ай бұрын

What is the difference between a task and a module?

@shivajeetiwari3816 10 ай бұрын

what is difference between ex-6.(a) and ex-2 ?? Why synthesis tool will do optimization in different way ,basically in such cases, how many Flip-Flop should be generated ??

@yukthiprasad3383 6 ай бұрын

Might be because: In ex-2 : Might be q2 and q1 both defined as output. In ex-6a : only E is defined as output.

@nagoomalnagm5127 10 ай бұрын

we want the file source of this piplined please

@randomyt5358 10 ай бұрын

Best sleeping Medicine ever

@huazero-r8o 11 ай бұрын

very good video, it really help my learning

@ericmaclean6254 11 ай бұрын

THANK YOU!!! love this course

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