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2:27 what happened here? Did you forget to divide Vs by L?

godsend

good video, but youre talking way too fast.

Can I get the link to this playlist? Thanks

Awesome vid

يعني حضرتك عربي ليه الشرح مش عربي المحتوي الانجليزي مفيش اكتر منه

fantastic video! :)

Very well explained ! 👍👍👍

Fantastic video! 👍👍 Just a small note: Custom-designed chips are known as ASIC (Application-Specific Integrated Circuits).

Hello Sir, Thanks for the videos! I would Know where Can I get this PDF

شكرا اخي انس صلاح الدين

Gem!

epic

Why is n-1:0 equal to 4 bits and not 3? Wouldn't n-1 = 2 and result in a 3 bit wide vector?

Thank you so much for this series. You saved my ass for my circuit analysis midterm

شرح ممتاز. ربنا يجزاك خير يا دكتور أنس

Amazing! thank you, Dr. Anas, can you please provide us with these files?

None of this is correct.

Sorry, i do not get the baud rate formula, could you clarify it again, please? Many thanks.

good Explanation with full clearity... Please, can u share the code or any reference to test...

Hi, One question on 2 flop synchronizer, the settling of metastability causes latency issue at the recever side, as for a signal changing from 0->1 at flop1 might settle to 1 or 0 before getting sampled by flop2, but will settle to value 1 in next clock So if it is settle in first clock the latency is 2 else the latency will be 3 How to update design to make this latency a fix value Considering both clock same frequency with phase difference

Why you added 1 and 0 with w_data in UP and I1 ??

the best video for synchronizer!!

last single port case should have an else statement, if there is no else statement it will be exactly like the simple circuit

when you mention hold time which hold time are you talking about r1 or r2

Which app you're using for the notes please, thank you.

Very useful video But you're very fast sir

Sir, have you made any video explaining the hardware resources in FPGA board like:GPIO ports, serial ports etc??

Does each line in non blocking assignment execute in different clock cycle

Hello Dr.Anas, Can this wrapping circuit interface with an analog/mixed signal component like an ADC/DAC/comparator with the system bus like AMBA bus architecture? Pardon my questions I’m still learning

Very good video! I would like to know however about the clocks u are driving each module with. Is ram updating with same 25MHz pixel clock? Btw, i understand memory is adressed even when in blanking interval, so u are sending pixel data on it too, since adressing is combinatory wo any video enable condition

cant think of writing a behavioural code for this yet

Hello Anas, great videos, would be possible to do a video on RRAM memory array architecture and is the memory is accessible to read and write Thank

THANKS

anybody looking for the test bench and the code - they are in his github under ece3300 repo, in module 9 files

Straightforward and very clear!

Thank you for your awesome explanation!

thanks for this

Tq!

Will changing the Switching Frequency, i.e Timer Value affect how long the counter will count for. I am having trouble where the counter will count to 255, but still be at 188 and switch duty cycles which causes a high. So it does not finish counting to 255 and resetting.

I think that loops in verilog aren't synthesizable But the generic one bit mux violates my expectations So, what it the state for my design code from synthesbility if I resorted to loops in

For the transmit, I don’t think we need the over sampling. Only the receiver needs the over sampling.

Good tutorial!

Hello Sir, Why did you decide to not have a FIFO in this design?

First time I see the whole process....gold mine😮

Thank you!

Hello Sir, Shouldn't the driver files go into the platform and application files in application project?

Where can I send you my question? Do you have telegram? Please 😢

Hi, I have a question Please I really have problem Can you help me please?