module basictest(input [0:0] sw, ouput LED[0:0] LEDR); assign LEDR[0] = sw[0]; endmodule

my questa windows didn't show up, why is that?

thank you so much

Its harder to get into intels licensing than fort knox 😞 And what have I done with my microsoft account 😞 Big thanks for your tutorial!

fucking GOD, thank you

Quartus-lite-22.1std.2.922-windows

this intro theme is also used by Mark Felton for his intro's, what is the name of this sound trackd?

absolutely great video thank you very much sir!

Thank you very much for the work you had making this amazing walk through and sharing with us.

Hi, very nice for installation and basic setup . I basic test for DE1 success, but for DE0-CV board not working Questa : # ** Error: C:/Users/..../Documents/Quartus/DE0CV/test.v(8): Module 'BasicTest' is not defined. # For instance 'bt' at path 'test' # Optimization failed # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0. # Error loading design

At 10:38, slide "How to use a block-based echo?" you say 1024 bytes, but it should be 1024 data points.

17:00 When I run RTL simulation after compiling code., I see error 'missing check nativelink log file ..." why is that?

Very clear instructions! I doubt I would have got very far on the confusing Intel site without your sage advice!

I don't remember these problems being so complex..... signed - old math major

Well explained, thank you!

Make more videos sir. Your videos are very easy to understand and to the point

Nice video sir

Fantastic Presentation You earned A Subscriber Sir.

thanks sir...perfect explanation!

Penmanship is sloppy, degrades presentation.

A good explanation !)

Hi. You should name better your vids. More need to see this good stuff.

Sir I tried in the same way as you did using Quartus 18.1. But during gate level simulation I faced following error. # ** Error: timing_8l_1000mv_100c_v_slow.sdo_typ.csd: syntax error, unexpected $end, expecting '(' # ** Error: (vsim-SDF-3445) Failed to parse SDF file "timing_8l_1000mv_100c_v_slow.sdo". # Time: 0 ps Iteration: 0 Instance: /test File: F:/Projects_quartus/timing/test.v # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./timing_run_msim_gate_verilog.do PAUSED at line 12

Are these chapters referencing a specific text?

see : kzbin.info/www/bejne/a2aTe36nmNpsm5o

Thank you. I understood this. It was a vague concept during class. thank you.

lectures on Image Processing --> kzbin.info/www/bejne/Z3Wkg2OwprSZeck

thanks

See my video on the same topic with a new perspective.

Good explanation.. I have also explained with all to gather different perspectives.

I want to know, Does it work accurately? If I can install only Quartus 18.1 lite without updates

Hi Jonathan, I was just wondering: 1. If we want to process/classify a periodic DT signal, we take DTFT of that we get something of the form (Impulse Train) times (Coefficients). We want to avoid Impulse Train and, hence, invent DFT, which will only give those coefficients without the Impulse Train. 2. If we want to process/classify a non-periodic DT signal, in order to take FT of it we need firstly to scale it by an Impulse Train. Then whatever the result we get is our classification. In order to avoid this scaling by Impulse Train, we invent DTFT which works directly with the samples of the non-periodic signal. 3. From these 2 points above, could you please tell me if my corollary is correct: If X[w] is DFT of periodic DT signal x[n], does that mean that X[w]*(Impulse Train) is the FT of the continuous-time periodic signal (Another Impulse Train)*x[n]?

Hello Jonathan. Thank you for the lecture, very insightful. If possible, would you be able to explain how one can arrive at the magical formula you've written at 9:26? I feel like IF I just got how to go from the weighted impulse train to the frequency domain representation it would be a big eureka moment for me. Cheers for the great lecture !!!

Didn't see that coming 1:10

When I am trying to install the Qartus then there are showing ' you don't have Quartus software installed in c: \intellFpga you need to have Quartus prime software installed in the directory

To get gate-level simulation to work, make sure the test bench module is in a file of its own.

I typed in your code and got this error any idea ? Undefined function 'release' for input arguments of type 'double'. Error in testaudio (line 13) release(dw); seem to be issue when release device writer

Hi sir, I dont understand the code out(i)=w(i+obj.Delay)+obj.Alpha* w(i) shouldn't it be out(i)=w(i)+obj.Alpha*w(i-obj.Delay) to follow same structure as the echo?

very good

Thanks for this video