#10 How to write verilog code using structural modeling || explained with different Coding style

[@no5x937]

Great tutorial! It cleared up a lot of questions regarding the using signal names and types for continuous vs procedural equations and the use of a hierarchy for test benches, top module, instances of sub modules. Thanks, JT

[@technicaldost9069]

You explained very clearly.thanks

[@radhikabandari4674]

your teaching is very helpful for beginners, thanks a lot.

[@ComponentByte]

This KZbin channel is for the freshers or beginners. So I always try my best to make things simple and clear and try to explain concepts and not just the theory. It makes me very happy when any fresher understands the content I have prepared.Thanks.

[@alonbechor1842]

Great explanation ! Note that the T-FF implementation is inaccurate, there should be a XOR gate in the feedback path with T and Q as input bits.

[@shivaninaik1693]

sir, you are the best .. very informative and detailed videos.

[@ComponentByte]

Thank you. Wish you a happy learning.

[@nityamaheshwari8259]

hii shivanii , i do courses of VLSI ,could you please give me your linkedIn i'd

[@bijaysah9135]

Every small concept is important in the world of chip designing. Thank u . I also want to learn test bench concepts, please make a tutorial...

[@ComponentByte]

Yes, I will make a tutorial on test bench concepts. I am uploading concepts serially so please stay connected.Thanks

[@circuitsanalytica4348]

Yes Bijay, test bench concept is rarely explained in KZbin videos. I will also make videos on test benches for VHDL as well as Verilog....

[@chintudewan1437]

wow, learned a lot.Thanks

[@ashutoshpandey3583]

Your lectures are really good. Please upload some examples using tool.

[@ComponentByte]

Thank you. I will do it once resources will be available .

[@circuitsanalytica4348]

Dear friend you can find some example codes in my channel.....

[@asraansari8854]

Hello. You provided good views & really helpful. One thing is please check the digital circuit of TFF and its corresponding Verilog code that you have discussed at the end of video. I guess it shouldn't be TFF, it should be 1 bit counter.

[@ComponentByte]

Thank you. Module t_ff code represents a TFF. Because tff is combination of DFF and an inverter. If this is the query then it's TFF .

[@rajatsen4105]

I got it . Thanks

[@BeMuslimOnly]

Good❤

[@tanuraj1928]

In fulladder module TestBench you take c as input and output both(line 10)is it ri8 to take same variable as input and output both??

[@ComponentByte]

That's my mistake. It's not c , it's cr Changing cr=%b will be fine. The Code I have provided for full adder including testbench is absolutely correct. The given code won't show you error. But it won't display cr value. Thank you so much for finding the mistake. Finding error is also a skill. Wish you a great career in semiconductor industry.

[@circuitsanalytica4348]

You cannot use same identifier for different ports or signals....

[@abhinavparri5084]

Hello sir, the module instantiations you made in full adder code work sequentially or concurrently??

[@ComponentByte]

Hi, every module instantiation works concurrently. Means all the modules are evaluated parallely and due to dependency we get delay. In real world also all hardware works concurrently.

[@teketinikhilkumar7905]

Sir, we have write the fadder4_str and fa29_bh modules in the same code right and while we are giving the A[0],B[0],C[0] in the fadder4_str it will assign to a, b, c in the fa29_bh and after evoluting return to sum[0] and carry out in the fadder4_str right

[@teketinikhilkumar7905]

Carry out I mean C[1]

[@ComponentByte]

Yes, you are absolutely correct.

[@susmithatalupula9791]

Could u please define what actually hardware meant by

[@ComponentByte]

Here it means the logic that we build using verilog code. After synthesis this logic is converted into a piece of hardware.

[@sathipaul182]

If you kindly share your .v file in text editor, it will be fine for practicing. Thank you for your lecture.

[@ComponentByte]

Welcome. No one asked for the code so far , so never posted the code separately.if you want the code of this tutorial , share your mail id and I will send you the code.Thanks

[@sathipaul182]

@@ComponentByte Thank you. This one is fine for me. [e-mail]

[@radhikabandari4674]

Hello, the outputs s, cr are declared as wire type, are they available in the next clock cycle/next output cycle. please clarify on input output types in test bench. please..

[@ComponentByte]

I have already explained the mistake in the video details section. Sorry for the mistake. It's not c , it's cr Changing cr=%b will be fine. Hope I understood your query. Thanks.

[@ComponentByte]

If something else you were asking then please let me know.

[@ravuruvasudevareddy3347]

In previous video u told that we should avoid behaviour modeling while writing verilog (But we can use it for writing test bench)..then why u have wrote @ 7.30 1-bit Fulladder in behaviour modeling?..

[@ComponentByte]

We should avoid doesn't mean we shouldn't write. When to write and how to write is more important. It's just a matter of generating hardware after you synthesize your code and if your written code generates desired hardware then it doesn't matter which modelling technique someone's followed while writing code.

[@ravuruvasudevareddy3347]

@@ComponentByte how cool u r..giving reply to all queries.....

[@rajeshrj4826]

Sir in dff code u have write "always" in structural modelling is it right to write always sir in structural modelling?

[@ComponentByte]

If you are talking about last portion that is T FF design then D FF is not structural it is just the instantiation of D FF in T FF logic and D FF is designed using behavioral modelling technique hence ALWAYS has been used. Please let me know if your query is something else.

[@rajeshrj4826]

@@ComponentByte yes sir I said about the t ff design.if we are writing in structural modelling for instantiation if we use behavioral model also is it right sir? Because in tff design we have use modules nd primitives so it is structural for dff we write it in behavioral model.so we follow this for other structural modelling for instantiation do we use behavioral model also?

[@ComponentByte]

Instantiation is not structural(it's used to design a logic) modeling. It's just calling the name of a module and this module can be designed either using data flow, behavioral and structural modeling technique.

[@rajeshrj4826]

@@ComponentByte thank u sir

[@yobyag]

How did you get cout like this logic

[@ComponentByte]

Can you please give more details like the timestamp and what exactly you are asking as I didn't get your query.

[@syedsibteali5761]

Sir i am not getting any value for Cr in Testbench output while all other value sum is correct after following your code is there any reason. module FourBitAdder(A,B,Cin,Sum,Cout ); input [3:0]A,B; // Its a vector input Cin; output [3:0]Sum; output Cout; wire C1,C2,C3; // the connections for Cin accors four full adders like C1 is putput carry of F1 and input carry of F2 fa_bh fa0(A[0],B[0],Cin,Sum[0],C1); fa_bh fa1(A[1],B[1],C1,Sum[1],C2); fa_bh fa2(A[2],B[2],C2,Sum[2],C3); fa_bh fa3(A[3],B[3],C3,Sum[3],Cout); endmodule module fa_bh(a,b,cin,sum,cout); input a,b,cin; output sum, cout; reg sum,cout; always @(a,b,cin) begin sum = (a^b^cin); cout = ((a^b)&cin) | (a&b); end endmodule module FourBitAdder_tb; reg a,b; reg c; wire s,cr; initial begin $monitor("SimTime = %g, a = %b, b = %b, c=%b, s = %b, cr = %b", $time,a,b,c,s,cr); end FourBitAdder dut(.A(a), .B(b), .Cin(c), .Sum(s), .Cout(cr)); initial begin #15 a = 1'b0; b = 1'b1; c = 1'b1; #25 a = 1'b1; b = 1'b1; c = 1'b0; #35 a = 1'b1; b = 1'b1; c = 1'b1; end endmodule here is the code

[@ComponentByte]

Can you please do modifications and compile again . Changes in testbench reg [3:0]a,b; wire [3:0]s; wire c; Let me know your result else I will try to compile it .

[@syedsibteali5761]

@@ComponentByte Thank you sir it worked.

[@ComponentByte]

Welcome. Keep learning 👍

[@circuitsanalytica4348]

Dear Syed, I cannot find any error in your code. Any way what was the problem.....

[@susmithatalupula9791]

Can't we write the tff code without instantiating

[@ComponentByte]

Yes, you can with behavioural modelling

[@apraveen3140]

sir i need xilinx and modelsim download link

[@ComponentByte]

kzbin.info/www/bejne/jH6oeoN5n9acpKM kzbin.info/www/bejne/gp-9qGtulJZ9b6M There are other links available in both Google and KZbin. If you type xilinx ise or modelsim installation on KZbin, you will get many links