#24 INITIAL block in verilog | use of INITIAL procedural block in verilog

[@navithapitla3429]

Good explanation sir😊

[@mughatoamugha9029]

Keep updating sir. Thank you for helping us

[@ComponentByte]

Welcome. Keep learning.

[@vishal_moladiya_music]

Too depth knowledge....genious bro

[@ComponentByte]

Thank you for your words. Keep learning .

[@adilbasu7183]

Nice concepts . Thanks a lot

[@minqingliang]

thank you so much for sharing! I have a question at 25:32 regarding values at #25, y should be equal to 1 as b = 0, right?

[@ComponentByte]

b value is updated =0 at 30ns Y value is updated = 1 at 35 ns At 25ns b= unknown and y= unknown because statement inside a initial block is executed sequentially.

[@minqingliang]

@@ComponentByte so basically, in an initial block, the value of the second delay depends on the first delay, like in the first initial block, the first delay is #5, then the second delay #25 means #(5+25) ?

[@ComponentByte]

Yes, as it's sequential. But if we write the same statement inside always block then 5 : assigned value 25: assigned value As inside always Statement are executed parallely. Thanks

[@minqingliang]

@@ComponentByte thank you! But I am a bit confused now, why "as inside always statement are executed parallelly", does it mean, there is no dependency of the previous delay statement #? Because in the video of Initial and always block, one of the similarities between initial and always is "all statements inside are executed sequentially"

[@ComponentByte]

No, inside always statements are executed concurrently so definitely there is no dependency. All statements are executed independently means . Let's say b=0,C=1 always 5 a= b+c; 10 d=a; 6 e=d; Here d depends on a value .e depends on d value 5 a= 0+1=1 10 d =a=1 6 e=d here e = previous value of d = initialized value of d = may be unknown as at 6 ns d value was not updated as d value is updated 1 at 10ns. Same thing inside always 5 a=1 15 d= 1 21 e =1 Hope it helps else let me know.

[@rajeshkrishnan1642]

i have a doubt sir, in every example program , inside the $monitor, u mentioned %b for every inputs and /n in previous videos what are they can u please explain?

[@ComponentByte]

%b is a format specifier to display binary data /n is for new line So every execution gives new line displaying number in binary format

[@rajeshkrishnan1642]

@@ComponentByte thank u so much for ur rply , I'm learning more frm ur videos

[@ComponentByte]

You are most welcome to ask whatever query you have regarding verilog or vlsi design. I will try my best to answer it.

[@circuitsanalytica4348]

Nice video....

[@ComponentByte]

Thank you.

[@alekhyakonuri252]

Wonderful explanation sir

[@ComponentByte]

Thank you.

[@digambarbhole9467]

hello sir , As you are saying, all the statements in the procedural block are executed sequentially (serially) but that will depend upon which assignment we are using na? if we use blocking assignment then there will be sequential execution and if we use non-blocking assignment then there will be parallel execution can you please clear this?

[@ComponentByte]

Yes , you are correct. But at real hardware level everything is parallel unless and until there is dependency in datas.

[@digambarbhole9467]

@@ComponentByte Thank you sir but still I am confused if in real hardware everything is in parallel then why we write code with blocking assignment and we says that it excutes in serial fashion can you please more elaborate it ??

[@alekhyakonuri252]

Stimulus means sir

[@ComponentByte]

It means inputs to your modules or design.

[@RoyAByers]

can you send your power point file to me?

[@ComponentByte]

So far I have never shared power point with anyone due to copyright issue, sorry. Anyother help ?