#3-1 Number representation in verilog || Number format in verilog

[@chandankumarbhatt580]

5'h75- SAYING SIZE IS FIVE SO WE LOSE THE DATA 011. WHEN 4'd13+2'd5=18 HERE WHY WE CAN'T LOSE THE DATA, AS I KNOW THE SIZE IS 4. Can u explain?

[@ComponentByte]

It will give incorrect result due to insufficient bits. The same i have explained.

[@gosuvo1706]

Even in 5'h75 - insufficient bits but we consider it from LSB then y not for other formats

[@gosuvo1706]

​@@ComponentByteor that concept of filling for LSB, only applicable for hexadecimal but not other formats??

[@madihasiddiqui4540]

@@gosuvo1706 Well i think the partial assignment happens in both cases its just stated in the video that it wont give correct results or outputs if 18 is stored in 4 bits it will become 8(=!18) hence it will give incorrect results

[@tirumalaraovlsi0667]

Your video is not visible

[@ComponentByte]

But it's clearly visible to me. Hope it's not some technical problem.

[@sanketsaxena570]

your wording and language messed up whole video you itself not able convey the concept clearly

[@tirumalaraovlsi0667]

It is total blurry