8-bit CPU control logic: Part 3

See eater.net/bbcp... for more.
In this video we use two EEPROMs to translate the instruction cycle ring counter and the contents of the instruction register to the correct control signals for each microinstruction. At the end of the video, we run the first full program!
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[@harrysvensson2610]

This has to be one of the highest quality video series I've seen here on KZbin.

[@ollimartikainen]

It is. Until you see his 6502 cpu series

[@videogametips5604]

For sure!! I've watched every single video in this playlist from start to end and I understand everything so far 100%! I'm sure by the last video I'll be able to build one of these myself with my own design (I have a different method of doing the display logic, and I have an idea on how to eliminate those wasted clock cycles on shorter instruction sets).

[@jeetenderkakkar7570]

100

[@thecrossedtheroadfund4289]

Harry, There is no way computers are as difficult as he makes them out to be. 👎

[@coloringontheline]

@@thecrossedtheroadfund4289 lol, what? "Computers" like all computers? Aren't as complicated as Ben Eater is making them out to be? As he describes his machine language operations on an 8 bit computer attached to a breadboard?? What does this comment even mean?! 😅😂

[@thelastofthemartians]

I'm glad that when everything didn't go as planned you didn't simply edit it out of the video. I think fault finding is just as important as design and implementation skills. Fantastic video as always. I'm really enjoying this series. Keep up the good work Ben.

[@virtimus2]

For me this is the most appealling aspect of this material. Really goood stuff :)

[@Trogwart]

But how to fill the gap between 'Primitive technology' channel and Ben Eater videos?

[@scitwi9164]

Step 1: invent metallurgy.

[@coolbionicle]

I think The King Of Random fits the bill!

[@DarthZackTheFirstI]

Maybe with a book written by ben eater! Title: From Transistor to the first PC. All those books (as far as i remember them) which are based on theory (i.e. about ALU) and technicality are horrible for teaching imho. Mostly because they lack a reference to reality and examples. there is for sure some potential.

[@giantneuralnetwork]

Stand on the shoulders of giants?

[@Sarioah]

Codys Lab and King of Random might be useful for this :)

[@danweecc]

Might want to add an additional control line to reset the micro-code clock when the instruction is done so save unused cycles.

[@MrWilliam932]

I was thinking the same

[@btharper1221]

That was a suggestion posted in the comments to the last video in the series, I think he was trying to acknowledge the possibility of doing so, without getting into the implementation for now. However he has mentioned adding more to the computer (including more control lines) in the future. I'd guess that he may want to finish the basic version to finish the teaching tool, then address some of the possible optimizations from the comments (adding CE to T1 was one such optimization that did get added already).

[@LordPhobos6502]

There's a spare output line on one of the EEPROMS, that could be used to send a reset pulse to the microinstruction counter :)

[@carroviejo80]

Nice idea, Im going to try to implement instructions as an FSM so it will not need that control line.

[@jonmayer]

I notice an output unused as well and thought the same thing.

[@revealingfacts4all]

I had a microprocessors class in college where we breadboard a MC68000, added memory, and then programmed it to do something but this whole series is immensely more educational than that college course. Thank you for these videos!

[@fingersmcoy]

i have learned more from this guy than any prof i had

[@3631162]

College is a waste of money

[@BillAnt]

Especially nowadays when a semester can cost $5k-20k uhhhh

[@michaelbauers8800]

@@3631162 Not for me it wasn't

[@DarthZackTheFirstI]

@@michaelbauers8800 you are still writing youtube comments!

[@dogtre2283]

But if porn isn't allowed on KZbin why are Ben's videos still online?

[@superidol4670]

wth do you mean

[@dankings5326]

I know this is 3 years old but just stumbled on this series the past week. Masterful work, so clearly and concisely explained. I've always kinda understood how computers work but seeing it in action really does bring a whole new dimension to that understanding. You really get a feel for how the first computers were programmed using punch cards! Obviously technology has moved on but the fundamental principles remain the same! This series really should be essential viewing for anyone wishing to study computer science! Or people like me that just love to better understand how the world works!

[@garydunken7934]

And there's the answer 42 again! Thanks for the video, I've been waiting for it.

[@scitwi9164]

I would be surprised if it would be something different this time :q It would mean that something is wrong with this universe :P

[@BrendaEM]

Now we have to find the question.

[@cpebud]

“The answer to the ultimate question of life, the universe and everything is 42.”

[@jeetenderkakkar7570]

100

[@robmckennie4203]

This has been a really excellent series, keep it up mate. Prior to watching these videos, I was vaguely aware of the fact that people build homemade computers, but never really had an interest in it, now I'm looking into doing it myself

[@WarpedFlayme]

You could use the last control bit to reset the step counter which would reclaim those lost clock cycles on ops that use less than five cycles. (I know the gains would be pretty minimal in this case (Only one cycle on three/one-step (incl/not incl fetch cycle) ops and zero cycles on four/two-step ops since the step-counter-reset micro-instruction itself would have to be a step), but it's something that would have exponentially larger benefits as your architecture gets complex with more steps available for each op. This is actually very interesting because it shows the benefits of a more complex architecture. By having more steps available per op (thereby increasing the complexity of the architecture; the cost), you can have more complex ops that reduce the amount of work the programmer has to do, as well as reducing memory requirements by reducing the number of ops required to accomplish a given task (the benefits).)

[@thehearth8773]

You could have your microinstruction counter reset take place on the last cycle of the instruction's operation, but that might require additional timing to make sure it worked right... A synchronous reset on the falling clock edge, perhaps, unique to this one control signal.

[@sly1024]

Exactly my thoughts!!

[@gelatinocyte6270]

It'll be nice to add a master reset button.

[@LordShadow144]

I was just thinking of suggesting to him that plus a command to reset; it could use that remaining bit on the instruction word after jmp.

[@gelatinocyte6270]

Yeah, That's a great idea!

[@12345NOU54321]

Brainyot building new computer to replace BAD PC

[@mandisaplaylist]

This is why normally you create a "control panel" with all the buttons you want to operate when not updating the wiring and just run really long wires between that and the places where the signals shall go. Also typically "setup commands" (like register reset or clock select) are placed on a top line and "operational commands" (like single step) on a bottom line. This will prevent the operator (you) from bumping anything. This is how the very first computers (like the Altair) were set up.

[@frognik79]

Please add a flags register, no cpu is complete without conditional branching.

[@John_2143]

he has conditional branching in his other computer via the overflow line on the ALU, and since he already has a jump signal I'm sure the next video will just be programming the rest of the signals and connecting that

[@cyruscarbone982]

I wrote an emulator a few weeks back. It's messy and slow, but it works. If anyone wants to help, the GUI needs to be worked on and accuracy checked. github.com/nutcase84/ben-eater-cpu-emulator

[@gzitterspiller]

I just downloaded all the videos from this guy, I guess I will keep it for when sociaty ends I will be the new Jack Kilby.

[@carrotsoup7264]

I hope one day i will be in front of this halt LED with a number on my digital display.

[@DarthZackTheFirstI]

so?

[@jimhalpert9421]

I love the editing in these videos. Speeding up the video in repetitive places while still having matching voice over must be a lot of work. But it makes watching much more pleasant, most times I don't even really notice the editing, which is the best kind of editing. Much appreciated!

[@williefleete]

My version of this CPU has been upgraded to have 256 bytes of memory about 36 instructions with a max of 63, two conditional lines with jump on (no) carry and (A!=0) A=0. Used the unused output on the 2nd rom for an external input, added a 3rd rom for microcode reset (and maybe further hardware) so shorter instructions only use as many clock cycles as it needs up to 7. The 256 bytes makes it prohibitive to manually program so I came up with a loader to pull a program off a rom on the IO bus so I only need to program 10 bytes manually and it loads a longer program in

[@protonjinx]

Put in some 74LS138 decoder/demultiplexters, 3-to-8 lines, one for output: RO, IO, AO, ZO, BO, CO, HLT and NONE. The other for input: MI, RI, II, AI, BI, OI, J and NONE. Two extra lines for CE and SU. 8 bits in total. Only one EEPROM needed. Part of the opcode 4 bits could be used to determine the length of the cpu instruction. Eg. all 1XXX instuctions being 3 steps, all 0XXX instructions being two steps.

[@christopherhite9050]

Ben, You are to be commended! I watched your entire series on building the computer, and I learned more than I learned in 2 years of computer science education at a top engineering school. Great job of teaching! I literally got tingles at the end of this video when the computer ran on it's own and halted. Awesome!!

[@hjups]

Since you mentioned additional functionality, have you thought about expanding the design to support larger memory spaces and instructions? You could easily modify the current design to use more cycles per instruction, make the address space 16 bit (by using two special 8 bit registers), and expand the instruction set to either use larger instructions (RISC style sort of like what the PIC16s do - other 8-bit MCUs might do the same thing), or adopt a variable instruction length CISC style with special registers (you are sort of already doing that, and it would mean possibly smaller code size at the expense of more instructions to define), or even adopt an already existing instruction set so that you can use already existing compilers (e.g. 8086, Z80, etc.). If you do that, you can then expand this series into memory mapped I/O, and then you also have the ability of taking the memory map and adding a MMU to deal with virtual memory. All of which should be doable using registers and EEPROMs as look-up tables (though it will quickly grow out of control in terms of breadboard space).

[@MrBluemoon74]

hjups that would all be possible but it would defeat the purpose of building the simplest computer possible for educational purposes

[@hjups]

I disagree. The ability to expand the design without significantly modifying the core "computer" would have significantly more educational impact. If you compare starting off with a more complicated design in mind (which requires a lot of starting knowledge), rather than the ability to transition into a more complicated design, then you would be correct. Right now, this model is a "toy" (in the academic sense), and can't really do much (especially with 16 Bytes of RAM). It would be a wasted opportunity to expand its functionality to teach more advanced topics. The mindset of keeping it simple for educational purposes is a pitfall that a lot of courses and textbooks encounter, and end up leaving a disconnect between the educational material and real systems. Unfortunately, only one of the courses I ever took broke that paradigm and ended up bringing the theory of operation back to reality (it was an FPGA based software defined radio, which could actually process an IQ stream and play audio). Keep in mind that I am not suggesting that the current design be abandoned, or that it should focus on a pipelined, super-scalar, or an out of order execution model, all of those things would defeat the purpose. A simple example of what I am talking about..... let the current memory address 0 correspond to main memory. Let memory address 1 correspond to the lower 8 bits of the address, and memory address 2 correspond to the upper 8 bits. Now if you want to read from or write to the 16 bit address space, you set the address by writing to the bus memory address 1 and 2, and then read / write from bus memory address 0. Then the only other step needed is to support a 16 bit program counter, which could be connected to a simple multiplexer switching between the bus memory addresses and the program counter, which is toggled during the instruction fetch phase. What has that done differently to this design? It made the program counter 16 bits instead of 4 (an easy extension), removed the program counter address from the internal bus, and changed the way the RAM worked, but not how it appears to the rest of the system.... The ALU doesn't change, if the initial instruction set supports read/write from/to the current RAM, then the instruction set doesn't change, and in fact, the control signals from the micro-instructions don't change. (The jump instruction might changed based on how it's implemented, but you could do the MIPS method and keep the upper n bits). And with all of that, you just expanded your computer from having 16 Bytes of memory to having 65K! Anyways, the point that I was trying to make is: the opportunity to teach more advanced topics based on the framework of a simple design is significantly more powerful than saying "here is a simple toy", now here is a real world case study, leaving the students (or in this cause audience) confused on how one went from the first to the second. And believe it or not, many computer engineering professors can't actually answer that question, because they never bothered to study systems outside of the "toy" setting (it took until a special topics graduate course for me to learn about how I/O is actually handled by a computer).

[@RussellTeapot]

+hjups I definitely agree with you, and I hope Ben will tackle on the expansion of this CPU.. The book he talks about in the first video (I can't remember the title, it was written by Albert Malvino) does exactly this: it starts from the SAP-1, and adds more and more functionality with the SAP-2 and SAP-3, basicly expanding what was built in the previous step. It's a marvelous idea and I'm glad I found these videos, I'm learning lots of things

[@OfMoachAndMayhem]

42! that's the answer - as it should be - On the next series of videos, we'll work out what the question is. Come back in... 6 million years XD

[@DanDart]

Logisim tells me that just the LDA, ADD and OUT instructions, encoded using pure logic would've needed 7 inverters, 5 3-input AND gates, 4 6-or-more-input AND-gates, 7 7-or-more-input AND-gates, 2 2 OR gates and 2 3-input OR gates. If we had to do it in purely 2-input NANDs, we'd need 149 of them.

[@Android480]

Its funny how quickly the "I'll build it all myself!" mentality goes away. I thought I wanted to do everything with simple logic gates, I know now that I really don't. Makes it tough to think about future projects though. Where do I draw the line? If everything needs to be abstracted, why not just go all the way and build an emulator in C++ or something.

[@DanDart]

Yes, it looks like it'd be a pain without the EEPROM which makes it significantly easier. What you need to make sure of is "What do I want to experiment with?", "What do I want to know / find out?" and "What do I want to play with physically?". You can just build all this stuff with enough patience in something like Logisim-evolution, but it won't help you debug real world electronics like plugging things actually will. I made a small Pi Pico W setup just to try out a shift register and LEDs and learn about things like pull-up and pull-down resistors. The real question is what do you want to get out of it? If it's just to emulate this system, then building an emulator is what you'll want to do. If it's to build it for real, then that. I also plan to emulate the CPUs used in Ben's videos in a public repository in Haskell, one of the best choices for good parsing.

[@MrWilliam932]

OMG yes 44 minutes of video

[@krokofan4425]

Never clicked on a video faster!

[@vijaykumarkanchukommala2183]

I think this is the best video to understand, how control unit works in computer architecture

[@DingleTwit]

I always say “E-PROM” so it cracks me up every time it sounds like you say “EEEEEE-PROM.”

[@fweephokus]

He's saying "EEPROM" (Electronically Erasable Programmable Read Only Memory), which is different from "EPROM" (Erasable PROM). The latter are the kind you erase with UV light.

[@Colecf]

At around 39:39, the computer starts loading undefined instructions, and starts putting multiple things on the bus. (Sum out and counter out are enabled simultaneously) Won't this cause a short and damage the components if a 1 and a 0 are placed on the bus at the same time?

[@CJBurkey]

I don't think it should, because the state of the bus when the input is taken should only be either/or, but not both as it's done on the rising edge.

[@CJBurkey]

Wait, +MrEdrftgyuji explains why it could a few comments below

[@barmetler]

@@CJBurkey well those tristate buffers connect the bus to ground at a 0, and to vcc at a 1. that means if one module has a 0, and another has a 1, one tristate buffer will connect the bus to ground, while another connects the same bus to vcc.

[@matthewe3813]

better hope all the magic smoke doesn't escape

[@PaulKooros]

You're exactly right, it's driving multiple contending outputs onto the bus (sometimes all five at once!). It's a good thing that these TTL parts are forgiving about "shorts" like this. Of course, TTL outputs have limits on the current they can drive. For that same reason, Ben is able to directly connect LEDs to outputs without a resistor (and not blow them up). That kind of thing is "minor abuse for the sake of convenience", and might cause problems like power supply lines being dragged down (and logic levels being lowered to indeterminate levels), but hey... FYI, most TTL-ish logic can source (push out a high logic level) much less current than they can sink (push out a low logic level). E.g. a 74LS32 datasheet I'm looking at shows source output current as 0.4mA, and sink output current as 8mA.

[@riddler2kone]

You are legend, Mr. Eater!

[@cryzz0n]

Ben, You are to be commended! I watched your entire series on building the computer, and I learned more than I learned in 2 years of computer science education at a top engineering school. Great job of teaching! I literally got tingles at the end of this video when the computer ran on it's own and halted. Awesome!!

[@ribvicky]

This entire series is mind blowing Ben!! More than 15years of wondering on "what exactly happens inside a CPU" ends here! Can't thank you enough for this. Started making my own now. Please try to make a video series on ADC & DAC because there isn't that proper info anywhere, because your teaching way is so beautiful, i believe that could help a lot to understand this topic. Respect 🙏🙏

[@mineyoucraftube1768]

for the dac you can use resistors and an op amp 0: 128k (lsb) 1: 64k 2: 32k 3: 16k 4: 8k 5: 4k 6: 2k 7: 1k (msb) i had this hooked up to the output pins of a shift register, the other side of the resistors were all connected together to the input of an op amp in a follower circuit

[@mouli570]

Today is my lucky day.

[@MrEdrftgyuji]

Need to be careful when executing "junk" microcode that sets more than one device outputting on the bus. If one device is driving a bus bit high, and another one low, you will have a short from Vcc to gnd which will probably cause damage to the chips connected to the bus.

[@Gaenkov]

Yeah, that part with executing a random junk from memory made me worry for the exact same reason. I imagine the troubleshooting process would be quite painful.

[@ared0hel]

An improvement on this design is to have a 3 to 8 line decoder control which register is outputting data to the bus, preventing bus conflict. This also frees up some control lines.

[@LeonardPauli]

@@ared0hel ...or using a demux for the enable signal // demux{input: instruction-register.bit-a, select: instruction-register.bit-(b, c, ...), output: enable for the various registers}

[@barmetler]

@@LeonardPauli or use an arduino to set all unknown values in the eeproms to 0b00000000, just to be sure.

[@markb7084]

@@ared0hel Good idea. Instead of direct control of lines it should be some sequential binary code (virtual address) decoded into control line indexes (each combination once in ROM)

[@paulrautenbach]

Excellent explanation again. Thanks.

[@jolesco]

Great video series, thanks for making these. That EEPROM based decoding scheme reminded me of the MOS 6502 decode ROM, showed in Michael Steil's "27C3" - "Reverse engineering the MOS 6502" Also the micro instruction timing was similar.

[@isbestlizard]

HEY it'd be pretty fun playing a VR game where you literally plug stuff into breadboards and have a massive bin of vr components you can pick from and they all work like they should and you could build stuff like this :V

[@howardjones543]

These last few videos have finally got it clear in my head what microcode actually is... really excellent!

[@nukeqler]

28:40 "Go back into program mode"--shouldn't it be "go back into run mode"?

[@azzajohnson2123]

parabozotics yep, good find, shows you were listening.

[@cmullins06]

Ben, thank you so much for these videos. You're a phenomenal teacher. Sort of fiddly question for you -- what kind of wire strippers do you use? Making all of these patch wires can be pretty zen, but it does get kind of exhausting after a while!

[@kindlin]

This awesome "thing we could do with this 16th output from the eeprom" is to implement the counter reset so that commands don't have extra wasted cycles. The 16th command (io0 on the right eeprom) could be to made to be 1 to reset the timer when the command is completed. The trick would be to not mess up your program by resetting the step too early. You could make this 'reset' its own line on the command table for a given computer command so that it only takes 1 cycle to finish off the current command (versus 2 wasted cycles on the OUT command, or more wasted cycles if we implemented a complicated command later), or, more elegantly, use the off-clock cycle pulse to check if this 16th bit is 1,and if so, then reset the steper to zero instead of incrementing on the clock tick. Hope I thought that through properly! I love all of your videos, they are amazing. Thank you!

[@jonyzhu6531]

"not mess up your program by resetting the step too early", that''s the point. A D-register may do the trick with the next clock pulse, if you still have room on the bread board.

[@philnelson2364]

You did something I've wanted to do since the 1970's. Every programmer should see this. Wonder if you can do a combinational logic cpu instead of a sequential logic version.. Also, the extra time sequence not used like "out" could be used to reset increment the program counter on the last micro instruction and skip t4, t5 etc.

[@peterwilson69]

I’m amused that breadboard wires the exact length and shape are constantly brought out as if pre-prepared : )

[@benbaselet2026]

Of course they are prepped. I think he built his computer first and then rebuilt it for the video series. Obviously one prepares presentations like this and does not just faff about for hours "live".

[@midnightrizer]

they were.

[@alshahriar6230]

R/whoosh

[@peterwilson69]

@@benbaselet2026 Oh... I kind of assumed that anyway - just very amused anyway. Wish I had an automated breadboard wire making machine.

[@matiastripaldi406]

Would it be possible to use a shift register chain, so you only need one eeprom?

[@amozizzle7566]

awesome video!

[@vladtepesch27546]

you could wire more than the 4 instruction bits to the eeprom, so you could support more than 16 instructions, because not all require additional parameters (out, halt, nop, ...)

[@happyfakeboulder644]

17:08

[@meepk633]

I've learned so much from this. Even things I knew before, I now have a intuitive understanding. Like why computers have to segregate memory for different functions. Thanks a lot. I can't wait to make one myself.

[@charlesjmouse]

Years late to comment, but still an awesome series. Thank you. Just in case anybody who cares is reading could the instruction set be further optimised to four rather than five steps? ...the last cycle in the 'ADD' command is redundant, and possibly confusing? Because the 'ALU' automatically puts it's result on the bus there is no need to explicitly load the result back in to 'A'. Indeed the extra cycle's commands only serve to screw up what is in the 'ALU', yes?

[@PaulKooros]

I don't think you can shorten it. If you make the {EO,AI} at the same time as the {RO,BI}, then the two outputs will both be trying to output data (and fighting over the value on the bus). It's all because this simple CPU has a single bus; first we have to move the memory value into B (over the bus), then we have to move the Sum result (over the same bus) to A.

[@IronRiviera]

Sure brings back memories. We did stuff like this in tech school in 1983. Good Job.

[@KuraIthys]

This has been fascinating so far. It's inspired me to try building something. (I mean I already had that thought, but now I'm considering other things, and trying it on a breadboard rather than a more permanent form. XD) If you're continuing with this much I'd be interested to see something like instruction pipelining. I have no idea how complex it is, but some rather old CPU designs had some minimal pipelining going on. Like the 6502 which loads and decodes one instruction while doing the first part of calculations for a second, and the final parts and data store for a third. (it's part of the reason the 6502 can even have some instructions that complete in just 2 cycles.) I mean, that may be too complex to sort out for a design like this, but a minimal 2-stage pipeline would be fascinating to see. (maybe those first two operations that repeat for every instruction could be the first stage, and the other stuff could be the second stage - that would not be perfect, but it would probably cut things down to 3 cycles per instruction at most. - and may still be simple enough to be possible to demonstrate on a design like this.) Personally, I may take on the idea of building a graphics chip rather than a CPU. XD Not a 3d chip obviously, but a basic 2d one. Seems fun. Tiles and sprites and stuff. - May have to cheat a little and give it a pair of framebuffers (which a design from that era wouldn't have), because I assume logic made from discrete components would be too slow for video output that monitors expect. With a dedicated framebuffer at the output stage, the main logic of the graphics chip could run as slowly as it needs to, and then write to memory, while the video output stage runs at the 25 mhz or so needed to output a 640x480 analogue VGA signal. (the system wouldn't be 640x480, but that's the lowest standardised VGA resolution, and is still supported by modern monitors if they have a VGA input. - You may be wondering if you're old enough how a VGA graphics card can deal with a monitor that only accepts 640x480, and yet run at 320x240 (or whatever other resolutions) - well, strictly speaking VGA monitors supported a handful of other modes, but the real trick is the VGA adapter is kinda lying to you. 320x240 is actually 640x480, but it draws every pixel twice, and every line twice. So, it outputs 640x480, but internally only has to do the calculations and use the memory for 320x240). Anyway, with the conceit that we have a double-buffered block of memory for the output stage, we could then build any kind of logic on top of that, operating at any speed, and it could switch framebuffers for the output stage whenever it's ready. Then we can build an old-style tile and sprite graphics chip (like those found in 8 and 16 bit consoles, and many of the 8 and 16 bit home computers from the 80's too), and however slow it ends up being due to the limitations of using discrete logic, it can still output a stable picture, just perhaps at an extremely low framerate. Unlike the 80's, memory, even SRAM (in small quantities anyway) is dirt-cheap, so we can get away with this pretty easily. Seems fun, right? XD

[@rafagd]

Could'n you have a "clear stepper" pinout that you can set as part of the microcode? That would allow the smaller instructions to reset the counter one cycle earlier.

[@stephanweinberger]

Or just use all 0 (which will never be a useful microinstruction) to reset the counter on the falling clock edge.

[@PseudoNo]

"Who knows what is it doing now" - Skynet is born. Great stuff! Thanks a lot!!!

[@vivek344ify]

Disliking these videos should be a felony

[@minecraftermad]

2-3 ipc holy moly catching up to amd fast

[@homloklebenyterapia9790]

Chernobyl control room simulator:

[@jaxey1631]

Really enjoying this series Ben, many thanks for taking the time to do it. I've been working in IT for a long time (almost 30 years), but never really understood how everything worked 'under the covers' until this series. I've enjoyed it so much I placed an order yesterday for all of the initial components to build one myself, although I'm planning on extending a bit once I get the base working (8+ bit addressing, multi-byte instructions, and maybe even a storage interface of some kind to load RAM from EEPROM or removable media). I had to use some substitutions for some of your parts list as they are hard to find - the 74LS76 (Dual JK Flip-Flop), 74LS189 (64-bit RAM) and 28C16 EEPROM - hoping I've understood enough that these work. Now just waiting for all the bits to arrive (no pun intended) to start playing.

[@Entarra]

I'm curious about the Halt command, that's a dead end isn't it? there is no way a computer (that relies on a clock signal) could ever undo this, seems very strange to me to have such a state vs a pause of some kind. That aside this has been an extremely informative series so far being almost exclusively a software person the hardware side of things have long been a mystery to me. and now I can count in binary so that's a plus

[@pev_]

Many CPUs, especially microcontrollers, have a halt command that is useful to save power. But usually the CPU continues execution when an interrupt happens (e.g. some peripheral wants attention).

[@tzisorey]

Needs to implement HCF

[@toolstime5136]

This is so cool to see the stuff running. For me it's the first time I understand how to program a cpu. Thanks so much.

[@okgoogle5028]

Konrad Zuse ( German. Build first programmable computer) would be proud.

[@lelandclayton5462]

I've been reading Build Your Own Z80 Computer by Steve Ciarica. I can't stand the King of Random.

[@justsomedude4660]

Lol

[@wbfaulk]

I feel like a NOR tied to step lines 1 and 2 that pull all the instruction lines low would allow you to avoid duplicate data entry for the two fetch microinstructions.

[@RicardoOliveiraRGB]

When I get money, someday, I'll assembly one of this computer...

[@justsomedude4660]

Its 100€

[@crateer]

@@justsomedude4660 but only with crappy and mostly unreliable breadboards :D but what you learn from this series is priceless!

[@RobertThz]

For you people harping on about a reset line for the micro instruction counter; did you even watch the video?

[@xXRedTheDragonXx]

Seriously dude! I love your videos! They are so awesome and entertaining!!! I'm very curious where you learned all of this information, because this is one thing that I would be interested in doing! Your channel is so under rated. You deserve more subscribers!

[@jeffreymusser8450]

I don’t see any resistors...pull-up or pull-down...But I saw them in the EEPROM programming video... When are they absolutely necessary?

[@mariogamer929]

Would it be possible to implement this kinda thing in a fpga where you only need to provide some memory?

[@PaulKooros]

Of course! intel/Altera, Xilinx, MicroChip, Lattice and a bunch of other new FPGA entrants all have "University" developer/evaluation offerings, some for a quite modest cost. There's not a lot of logic in this design, so it should easily fit into even a small FPGA.

[@massimookissed1023]

Surely your *HALT* control signal LED should be red ? ;)

[@HaydanF]

What happened at 32:44 his arm went over the LEDS and without doing anything they change?

[@danbopes6699]

Looks like he may be hit the load signal on memory register, as it transferred what was on the bus to the memory register.

[@다이아몬드곡괭이]

Hello Ben, im a 13 years old kid Your series is amazing even a kid can understand how it works!! thanks for this amazing video, and now im making a computer at home!

[@SiliconSet]

Great video! Many thanks.

[@infl]

Did you design the set for Star Trek: next generation in a past life?

[@iProgramInCpp]

Ben Eater's computer specs: 16 Bytes of RAM 2K EEPROM for Left instr. 2K EEPROM for Right instr. 2K EEPROM for Display A Register B Register Out Register Sum Register Many switches 8-bit Data Bus 4-bit Address Bus/Program Counter

[@sampathsris]

I was wondering if we could add a control signal to reset the microcode counter to save time on shorter micro instructions (say "MR" for "Microcode Reset"). LDA would look like: CO MI RO II CE IO MI RO MI MR Could this stop a cycle being wasted? Or am I missing something?

[@LearningCS-jp4cb]

In instruction cycle, fetch stage was labelled at appropriate places, but i felt other stages like "decode, execute" were jumbled.

[@ErebuBat]

This is the FIRST TIME i have actually understood what CPU microcode actually is.

[@alammd.samsul8424]

ei chainese board golo to valo na lohar toiri kokhono connection pai kokhono pai na......ei board goloki valotype er powa jai? r pin push korar hole golo sqere kano?......amd.

[@hubertk7363]

Why in 31:00, RAM address has reset, when instructions were RO and AI? EDIT: he just accidentally bumped the memory reset signal (one more time)

[@mistervoldemort7540]

Before I was bored on KZbin, but that was before I discovered this channel.

[@jarisipilainen3875]

i have computer too,but i think its more clever than anyone can imagine. NOP 1 clock cycle LDA #$14 2 clock cycle LDA $14 3 clock cycle. you ask how is possible. well read from memory that is pointed program counter. vola we have it on instruction register. we know put it in there becouse we know we read instruction.microcode was alleready setup on reset (and after we done other OPs) next HALF pulse we change microcodes according to OP code.increase counter. reset instruction counter(if NOP example) 2nd clock cycle we know its data.it go directly where it need go. in this case Aregister. next HALf clock we change microcodes again to fetch instruction. reset instruction counter.increase program counter. 3th clock cycle is needed if data is read from memory,but it go directly to a register becouse microcode was changed on 2ndclock cycle. and every thing is reset. 3 cycles is maxium i need ben might know how do it. only need small delay after rising clock cycle to latch data destination register.down clock cycle microcodes can change,becouse nothing will happen same data not latch example in B register becouse we not rising edge. thats make it clever,but you could think it as its just double clock and i use rising edge and down edge.maybe its cheating lol

[@calmchess0434]

GPU manipulates ram by sorting it then processes it in a stack. I think Intel must sort ram process it in a stack and hyper excite the clock....that's my theory. 1/8/2022

[@haridaniel777]

32:43: You also bumped the mem addr reset wire.. :D I was looking multiple times, why the address changed magically after your moved your hand over it... :D But that didn't caused any problem... Later I saw your note of the second bump, that caused problem actually...

[@benjaminschabel4847]

I am tired. I need to get up early. My eyes hurt. Why is it i cant leave?

[@DBuilder1977]

Of course it had to answer 42. All great computers have an answer of life, the universe and everything of 42. In most other computers however the question is unknown. In yours it's known. kzbin.info/www/bejne/l5PSi5aqp62ZgZo

[@fifaham]

@39:35 without HLT CMD got 42 then garbage - @43:00 With HLT CMD we got 42 then STOP - Amazing - lets ship it LOL

[@pareshmhatre4019]

Mr Ben, i really don't know why you choose 6502 mp, and not upgrading your own breadboard computer for further videos!

[@cLxJaggy]

How about using the last free data bit of the EEPROM to reset the micro-instructions counter? This would allow the number of steps to vary along with the instruction executed as needed, saving computer's clock's cycles!

[@thumper88888]

Would it be overkill for micro instruction, 0 OR 1 to cause a buffer to switch the instruction to the ROM low ? That was a lot of dip switching. 😳

[@nadie9058]

The most important thing is, the EEPROMs are the libraries

[@lb5tr]

Do you plan to create a assembler and a some simple high level language?

[@mattclifford8181]

does anyone know if i can use the at28c16-15 instead of the at28c16? i cannot find a reliable at28c16 vendor

[@raingerliu319]

there should be a state. after you reset, the clock pulse could be either state, then either would the step counter be first triggered or other modules. in this video, the program in RAM just passed this problem that's why everything seems just fine, and that's because after you reset, the RAM addr would be 0000, and that's what exactly the first step in the program gonna do next. if you just step over the first step and that means a falling edge of the clock coming first after reset, in this program, you catch nothing flaky. and when it is a rising edge coming first, still because in fact, it does nothing(put 0000 into 0000), nothing goes wrong. so it seems the first step is not only necessary for after going but also works as a ' reset booter' it does nothing if there is a rising edge first, and when you skip it in a falling edge first, means you skip nothing neigher. so no matter either state coming first, it should work fine.

[@footballCartoon91]

@2:26 So there are two kind of programming one is the normal programming using other computer.. And the other one is programming like in this video. I.e in every "bit state" of the input there will be some pattern of each of the output bit?(i dont know)

[@rarrmonkey]

if you consider only 1 signal should output to the bus, you could take 3 output pins and decode them into 7 control signals + 000 = no output to bus. I know it's not enough to reduce the required pins to 8 but it would prevent double writing the bus.

[@elalemanpaisa]

couldn't we just reset as well with some logic gate when a particular instruction doesn't need as many steps? doing nothing doesn't sound that nice tbh

[@robertwilsoniii2048]

Now I know how roms are burned. I see now that programming in the software sense is just control logic for the processors of the computer, or compiling anyway. And manufacture assembly code is the hardwired control logic of the processor. I wonder how hard drives communicate with program counters to deliver code to control units of a processor.

[@patrickleboutillier]

When using EEPROM chips like this, is it possible that the EEPROM sends out the wrong control signals for a very short period of time when the instruction or step changes?

[@QDWhite]

Hyperintelligent, pan-dimensional beings: we need a earth sized supercomputer running for 7.5 million years to determine the ultimate answer. Ben: have I got a video series for you!

[@muxahx3096]

in case of apocalypse i know how to programe EPROM from sticks and stones....

[@thisismissem]

Is there a reason not to do a logic NOR on the highest two bits of the step, as those are always contain a 1 for a step that's not loading the instruction / incrementing the step counter, and then do an AND on that and the instruction bits; that way you don't need to use memory for all the fetch steps repeatedly? It's a little more complicated but makes the computer easier to program (I think I got the NOR and AND operates right for the matrix you had there)