9.20. Memories in VHDL

[@mahmoudtantawi93]

if the latched output which is the middle choice is in a clocked process, wouldn't it be translated into a register? I understand that dout will have to keep its old value if WE=1, but I thought that unwanted latches can be generated in combinational processes only due to some missing conditions.

[@electrontube4284]

There is a missing condition. In the bulk of the if, we only assign the memory content. In the bulk of the else, we only assign the output port. Thus, the output port is missing definition in the bulk of the if, which creates latching for the dout bus. If the problem here is whether this is a latch or a register, then yes it depends on whether the process is clocked or not. In asynchronous memories, it will create a latch, in the memory we described it will most likely synthesize into a register.