A new look at MOSFET turn off loss

[@biswajit681]

Excellent.....sir could you please make video on Active clamp forward converter operations and it's design

[@sambenyaakov]

There is a video in my channrl on active clamp for Flyback

[@anoimo9013]

Nice trick. Good use and example of simulators

[@sambenyaakov]

Thanks.

[@owieccyt]

We just published a paper on measuring the turn-on and turn-off losses (title: calorimetric measurement methodology for comprehensive soft and hard switching loss characterisation). We can directly measure both turn-on and turn-off losses at hard and soft-switched conditions. We do all that without a current shunt or impacting the switching loop. The paper is not yet indexed but if someone is interested I can send a copy.

[@sambenyaakov]

Interesting. Can you send me a copy? [e-mail]

[@fala-at]

Could give the link to the paper ?

[@sambenyaakov]

OK

[@aprilzhao360]

Great explanation on the MOSEFT switching behavior. One question, considering the channel loss and Coss E stored as a whole during MOSFET tuning off, how does the dependency on inductor current look like? Is it still the higher the IL the less the total loss but with less correlations factors, or no change on total loss?

[@sambenyaakov]

Good question. The inductor current is controlling dv/dt. The higher the current the faster is the rise and the overlap.

[@mehtabhussain4961]

​@@sambenyaakovdo you mean to say that at higher currents , voltage will rise steeply, therefore overlap between falling current and rising voltage will increase therefore increasing channel loss ? On the other hand, for low inductor current, the voltage will rise slowly and therefore low losses ?

[@sambenyaakov]

@@mehtabhussain4961 Indeed

[@kkh8623]

Hello Prof.Sam. What a wonderfu lecture.. Can you explain why the current direction of the upper Coss is like that? should be it opposite way? 9:21

[@sambenyaakov]

Yes, you are correct. This is an error. The arrow is in wrong direction. Thanks for pointing this. .

[@m_dunn]

Great explanation! Have you already done the hard on switching explanation in a half bridge, or is it to follow?

[@sambenyaakov]

In the making😊

[@vasilisk8944]

Wow, thanks!

[@sambenyaakov]

👍🙏

[@gsuberland]

Would the accuracy of the simulation in this context be improved at all by switching from the Shichman-Hodges model (level 1) to an alternative model such as MOS2, EKV, or BSIM? I know the latter two are designed for submicrometer ASIC applications, and may be difficult to set up from the datasheet alone, but the improved modelling of subthreshold behaviour seems to imply that they might offer improved accuracy in the context of switching losses. I'm less familiar with MOS2 (and MOS3) but they look to be very easy to set up. Additional question: is there any non-negligible internal parasitic resistance (or another source of thermal loss, such as we see with domain wall heating in MLCCs) in the internal Coss path during switch off? If so, is that at all relevant in the hard or soft switching cases? (presumably not in hard switching, since the energy is lost into the channel anyway, and only fractionally so in soft switching due to external parasitic losses dominating the picture)

[@sambenyaakov]

Good questions. 1. I really don't know which model is th best. I am using models supplied by the manufacurers assuming that they chose the best MOS model. 2. Dielectric losses were documented for super junction transistors, I doubt if it is significant here. Thanks for the conversation.

[@robr8554]

Can you show how the 6 in the denominator occurs?

[@sambenyaakov]

kzbin.info/www/bejne/mZuzfoWpe6ydabs

[@mahitvirma]

Prof in the circuit at 00:10 if the diode is conducting the voltage across the top mosfet should be clamped to +hv so i can't see how vds voltage and id current can change simultaneously Thanks

[@sambenyaakov]

Did you see this? kzbin.info/www/bejne/fWGQg3aIq8lsprs The voltage is controlled by the caps charging. If you don't follow, let me know.

[@kundansrivastav8711]

Hello Prof @@sambenyaakov. I had the same question - I was also expecting HS FET's VDS to rise completely before ID starts dropping. But after I rewatched the time stamp you are referring to, I could deduce this - In the case where HS turn OFF is FAST, in that case the COSS of HS starts carrying current, which slowly charges it up (raising VDS) while channel current ID is dropping Is the understanding correct? And if so, do we mean to say that IF the HS turn OFF was SLOW, in that case we would see VDS rising fully first (and LS diode starting to conduct) before HS ID starts dropping? Thank you.

[@tanmayvadhera4250]

But the source voltage is free to change

[@sambenyaakov]

@@tanmayvadhera4250 The source voltage is not " free to change". The source voltage is dictated by the external circuitry. A MOSFET is a current source not a voltage source.

[@tanmayvadhera4250]

​@@sambenyaakovDear Prof, I actually meant to say the same thing, as in the drain is tied to the supply and the source is free to change based on the load (as you mentioned) .

[@tamaseduard5145]

👍🙏❤

[@sambenyaakov]

thanks

[@gaynzz6841]

How many more "new looks" will there be? lol

[@sambenyaakov]

Do you have anything of substance to say about the content? Or your attention span does not extend beyond the title? lol