DVD - Lecture 5f: SDC Continued

[@hujiawei5196]

how do we choose/set the parameters in these constraints

[@AdiTeman]

Well, that's the $64,000 question :) In general, the constraints come from a few places and from a lot of experience and "guesstimates". To start, there is usually a spec, i.e., some frequency that your design has to meet. That will set the clock frequencies, which are the most important constraints. Second, you have some recommendations by the fab or by company policy for what kinds of "derates" to apply to account for jitter, OCV, etc. Third, you have the I/O constraints. These can come from all kinds of places. For example, in hierarchical design, the best thing is to "push them down" from the top level. So you would design your top level, place and route it, and then see how much time you can budget for each sub-block. Then you can push down the SDC constraints that you need to put on the I/Os of the sub-block to account for these. Unfortunately, in many (...most?) cases, this doesn't happen and you have to go bottom-up and decide how much to budget based on your acquaintance with the higher levels. Often you start with some default value (e.g., T/2...) and then see how much you can push the design or how much budget you need and then communicate it to the toplevel and other macro owners. Other things like false paths, multi-cycles, etc., come from the designers and require a lot of collaboration with them. Often they come from previous projects and you have to double check that they are actually right and appropriate for the current project. I hope that clarifies this a bit.

[@kunliu5004]

What's the constrained logic in 13:00? Why do we need this block? What's the function of the block?

[@AdiTeman]

I think you may have misunderstood the point here. Let me elaborate. We need to constrain all the logic in our design. Constraining the reg2reg paths is "easy" (or at least straightforward). All we need to do is define a clock and we have all the data we need to calculate min and max delay constraints. But our "block" also includes in2reg, reg2out and in2out paths. These are not fully constrained with a simple create_clock command. For in2reg paths, we know nothing about the launch path until it reaches the block input. For reg2out paths, we know nothing about the launch path from the block output and on. We also don't know what happens to the clock (capture path) outside the block. Therefore, we need to add SDC commands that will constrain these paths. In the figure, the parts marked "constrained logic" are inside our block and so we can sum up the delays. But once we leave the block, we have to use SDC to model what the delays (or rather, constraints) are outside the block. I hope that clarifies it.

[@Shahidsoc]

different cells have different transition, so which value shoul be chosen from which cell's table ?. and what to do if we have CCS model libraries.

[@AdiTeman]

Hi. I'm not sure I understand the question exactly, but I'll try to answer. If you mean what to set as a default input transition - this is a good point. We want to model the input transition, but we don't know what is connected to the input and how. Therefore, the calculation will not be accurate. This is a limitation that cannot be overcome, but the point here is to get a "good estimate". In general, digital delay modeling is NOT ACCURATE (as opposed to SPICE), but provides a tradeoff between run-time and accuracy. So we are trying to get a number that is "good enough", while it is clear that this is not 100% right. In this case, we have two options - 1) provide a number that characterizes the process. This is very inaccurate and has nothing to do with CCS or the different gates. It's just some number that could be a reasonable transition so the delay of the next gate falls within the timing tables. 2) provide a typical gate from the library that may be connected to the input. In this case, the .lib (including CCS) of the gate is used for the delay calculation. This is not the gate that is actually connected, but is typical of the technology/library and therefore is a good estimate. In any case, these are just estimations. Not accurate. But better than assuming something that is not based on anything...

[@umarnadeem4074]

can you recomend some textbook for this course as well?

[@AdiTeman]

Hi, Actually, that is not an easy thing. I don't know of any comprehensive textbook that provides everything I cover in this course. That said, there are many books and other material that you can find that together will provide everything. What my main suggestion is, is to look at the list of references at the end of each lecture. I have tried to put the main sources that I relied on (other than my own experience and knowledge), so for each lecture, some relevant text book may be available.