Carry Look Ahead Adder (CLA) Explained

[@ALLABOUTELECTRONICS]

For more information, check Digital Electronics (Playlist): kzbin.info/aero/PLwjK_iyK4LLBC_so3odA64E2MLgIRKafl Timestamps: 0:00 Limitation of Ripple Carry Adder 2:00 Carry Generation and Carry Propagation logic in CLA 4:40 Carry Look Ahead logic for 4-bit Adder 10:28 Delay Comparison between Ripple Carry Adder and Carry Look Ahead Adder 13:30 Limitations of Carry Look Ahead Adder 14:52 16-bit Adder using 4-bit CLA blocks

[@anushkasaxena590]

I'm honestly so so so grateful to this channel and this person! You not just made me score good in exams but made me understand the deep meaning of concepts. Thank you very much, truly grateful to you!

[@poojakhanna6942]

This tutorial explains it better than any other one I have watched. Thank you so much for the tutorial.

[@shivaram6991]

my soul left my body after trying to analyse the last circuit design

[@Motion-Studio]

mine alsooooo

[@HogenkampNick]

10:28 Gx and Px should be switched in the Carry Look Ahead Logic Circuit block.

[@DhrithikRaj]

Yes. Thanks for this!

[@jackey-mill3634]

Yeahp

[@trunghieule758]

Everything is fully explained. Thank you!

[@awaviarybangalore]

Complexity explained in the flow of water, hats off sir.

[@Stevensmith30247]

Very Perfect Explanation for the CLA

[@user-jq2cx3sq3q]

So smoothly presented! Thank you!

[@kalebm1279]

I am literally in love with you now I can finish my homework

[@PalashKantiKundu]

Beautifully explained.

[@mayurshah9131]

Always enjoying your posts

[@meanpillscasper]

Fantastic explanation, thanks!

[@Ansari-go5dr]

Straight to point explanation... Go ahead sir🥳

[@vincecs]

This was an amazing explanation👍

[@NightVisixn]

Very good tutorial man, thanks for the video

[@user-ed6ho2om7x]

the last circuit for CLA is bit complicated to understand for me can you please explain it

[@user-ye7hw7qr5c]

I hope you can explain the last two-level carry-lookahead.

[@nverkhachoyan]

Amazing video! Thank you so much

[@theawes0me0ne]

Thank you very much, i finally understand the gate logic behind CLA adders. Been trying to learn the gates to make a faster binary adder in a game.

[@urmilareddy6047]

Wonderful explaination....🔥🔥🔥

[@rafikfarhane713]

whats about the delay in the last clag ?

[@lymtics88]

I'm confused cuz on Harris&Harris textbook, Propagation is A+B(i.e. A or B) but not A xor B, why is that?

[@uyioduware693]

Is it not supposed to be 3 gate delays, because it waits for 3 parallel gates before it's passed to the final gate for implementation. Like the 3 parallel gates are delaying the calculation in the final gate.

[@mohammedsameer3012]

time 10:23 in the video there is mistake that is you took P as carry insted of sum. specifically in P1, P2,.....

[@kartiii_45]

What is P ? Propagation P=A XOR B right..... we will get that separately but as you said, at mentioned time stamp as per the CLA circuit diagram, it is generating carry as C1,C2,C3..... .The Main flow will be ----{P & G Generation=CLA=ADDER}-----. The sum Output must be A XOR B XOR C(Carry) .

[@akshithlyrics2504]

Sir can you explain me about gate delay . Why it is 1 gate delay & 2 gate delay ?

[@RanokFerdous]

awesome

[@TheRojo387]

So synchronous carry is actually carry lookahead…

[@maximekahn]

Which adder is currently implemented in the industry?

[@jacks6910]

Both

[@jacks6910]

The benefits and drawbacks to each both have a place for specific tasks.

[@user-dl8sc6hy2s]

I am having very informative time to listen your lecture but I cannot lie that I haven't noticed your intonation. Are u indian robot? I am sorry If this offends you. I love your contents!!

[@Mo__Ga]

Also immediately noticed, the way sentences are always ended on a low pitch along with the strange pauses in between reminds me of early text to speech.