Is Length Matching Required in High Speed Buses? - Altium Academy

[@wiehannbotha3384]

Thank you for the great information. I have in the past used length matching for busses, but have in the last 5 years moved to TOF(Time of flight). Would lthe assumption be correct to say that TOF is a better way for matchin legnths? I match my tracks to 1ps accross the bus, this seems like a overkill, but when I match tracks, I found that matching to 1ps and matching to 100ps is the same amount of effort.

[@Zachariah-Peterson]

TOF is the objectively correct way to match lengths. As long as you can calculate the time difference, you can calculate the length difference, and then you can use the length mismatch constraint.

[@DiegoColl44]

Again, thank you very much!! good information.

[@EfieldHfield_377]

Thank you for positing. I found your assessment a bit difficult to follow, my bad not yours. If you can please humor me by reviewing my example question that would be most appreciated. So assume my bus is made of address, data, and control and has a clock rate of 100MHz. So to center the address, data and control on clock the allowable time margin would be ½ the clock period or 5ns. If I estimate my velocity of propagation on the PCB to be 150mm/ns (about 6”/ns) then the distance traveled per 5ns would be 750mm. So in this example for my address, data and control to be perfectly in sync with the clock would require ALL lines (including clock) to be 750mm long. Conversely, since this is such an abnormally long length if actually PCB trace lengths were non-equal, but for the purpose of this example the longest of which being 200mm, and the shortest 150mm, then I would assume the time / distance to be non-factor and as such only take precaution to ensure the clock was the longest traveled signal (say 250mm). Is this assessment correct, if not can you please point out and correct were it goes wrong.

[@Parvi_]

I believe the calculations are needed in a data bus where the data speed is too high, or atleast more than or equal to 1Gbps, where the bit period is too small and we cant afford any small skew. 100MHz clock rate is not a fast enough period that require strict length matching, it has enough time marging for both data and clock lines and the designer is not bound to tune the length of the clock line exactly in Middle of data line period. Even in few DDR2 layouts that run maybe at around 250MHz, clock and data lines are seen to be routed normally, no length tuning is done and work perfectly. To sum up, the more the data rates go high the less the time margin we get and so we try hard to match the clock line so as to make its transition happen in the middle of data bit period where we assume the data bit to be in most stable condition.

[@EfieldHfield_377]

@@Parvi_ Thanks for your response. The example was not so much about overall bus speed but concept. The point is you could make just about anything reflect or skew, given enough physical distance comparing point to point or route to route. I was trying to verify the calculations of my electrical distance (wave length) in my media of propagation against my physical distance as the placement of memory and processor were not ideal. I saw the video and asked the question for due-diligence sake. LOL, never did get an answer until now, but thank you for your generous time and response. You make an excellent observation regarding overall clock speeds and application that are both useful and pragmatic - Much thanks.