Architecture All Access: Neuromorphic Computing Part 2

In Neuromorphic Computing Part 2, we dive deeper into mapping neuromorphic concepts into chips built from silicon. With the state of modern neuroscience and chip design, the tools the industry is working with we're working with are simply too different from biology. Mike Davies, Senior Principal Engineer and Director of Intel's Neuromorphic Computing Lab, explains the process and challenge of creating a chip that can replicate some of the form and functions in biological neural networks.
Mike's leadership in this specialized field allows him to share the latest insights from the promising future in neuromorphic computing here at Intel. Let's explore nature's circuit design of over a billion years of evolution and today's CMOS semiconductor manufacturing technology supporting incredible computing efficiency, speed and intelligence.
Architecture All Access Season 2 is a master class technology series, featuring Senior Intel Technical Leaders taking an educational approach in explaining the historical impact and future innovations in their technical domains. Here at Intel, our mission is to create world-changing technology that improves the life of every person on earth. If you would like to learn more about AI, Wi-Fi, Ethernet and Neuromorphic Computing, subscribe and hit the bell to get instant notifications of new episodes.
Jump to Chapters:
0:00 Welcome to Neuromorphic Computing
0:30 How to architect a chip that behaves like a brain
1:29 Advantages of CMOS semiconductor manufacturing technology
2:18 Objectives in our design toolbox
2:36 Sparse distributed asynchronous communication
4:51 Reaching the level of efficiency and density of the brain
6:34 Loihi 2 a fully digital chip implemented in a standard CMOS process
6:57 Asynchronous vs Synchronous
7:54 Function of the core's memory
8:13 Spikes and Table Lookups
9:24 Loihi learning process
9:45 Learning rules, input and the network
10:12 The challenge of architecture and programming today
10:45 Recent publications to read
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[@AlexSchendel]

Very cool technology! Looking forward to seeing where Loihi and LAVA end up! Impressive that Loihi 2 was ready to go on Intel 4 so fast! From what I can see though, the extra density you gained versus Loihi on 14nm went towards a much smaller die size. Are there plans for something like a Loihi 3 that might scale the die size back up and tackle some larger networks? I also saw the stack-able Kapoho Point boards were released a couple months ago, but there wasn't really any press on that, it would be interesting to hear more about that. So there are four Loihi 2 chips per Kapoho Point board and you can stack multiple boards for 8, 16, potentially even more? I recall there were full server racks with over 700 Loihi chips in them though. Is there any plan for that sort of scale with Loihi 2? In any case, very cool stuff and I think the most interesting thing of all would be to see what this sort of technology enables. Loihi had some interesting graphs showing how it stacked up against more traditional accelerators and such, but I haven't seen that for Loihi 2 anywhere.

[@DukeAbbaddon]

Brilliant!

[@aaronmatos5581]

Niceeeeee! I was expecting this! Thanks for the information!

[@fpgamachine]

Amazing, wonderful. I would like to buy a development board with one of those chips.

[@drewgonzales6969]

great presentation.

[@dmkdata]

Great video. I'm very curious to see where neuromorphic hardware finds its first commercial application.

[@ALEXGIBSONCMG]

out of the corner of my eye your icon looked like the Drumsy channel icon for a second.

[@SaiyanGokuGohan]

A company called Brainchip are the first and only commercial neuromorphic company and Valeo and Renesas are bringing out applications end of this year (2023) Valeo’s Scala3 Lidar and renesas and multiple applications

[@centuriomacro9787]

Its fascinating that biology created such a performant power efficient computer like our brain. Youre work at Intel is very exciting and inspiring.

[@Nissearne12]

Is there any evaluation board avaleble to buy and play around with. Neuromophic chip seems to be very exciting things.

[@josephvanname3377]

And what about reversible computation? When are you going to work on reversible computation? When will we at least get energy efficient reversible LFSRs?

[@DukeAbbaddon]

10:12 Encore! RS

[@jdog5362]

Akida 1000 more synapses

[@customknives5035]

Akida 1500😉

[@and_I_am_Life_the_fixer_of_all]

16th!

[@IngeniousDimensions369]

Cool…🥹🥹🤓🤓

[@darylallen2485]

Crysis? 😂

[@nyhammer1]

KZbin is getting filled with AI generated content ...

[@techaido]

Great talk and smart guy, but he doesn’t give himself enough credit, saying that evolution (which is NOTHING (it’s just a theory) is more intelligent than him. 1:00 THE PERFECT CHIP DESIGNER Is GOD otherwise stop working on your design, because with time it’s just going to evolve into the perfect chip.

[@DukeAbbaddon]

{Solve} : {{Maths Roll Error on 24Bit Audio versus 32Bit} ~= Stutter} : Windows 3D Audio, DTS & Dolby Atmos 2022-11-30 RS * {Solve} : {Maths Roll Error} : (c)RS {Maths Roll Error on 24Bit Audio versus 32Bit} ~= Stutter Additional roll, Error margin on 32Bit maths Float with 24Bit 5 point margin roundups, A 32Bit float rolls up on a single operation 226526554817.{24Bit float + Error roundup} .9> .49 = .5+ = roll up.. R={5+ or 4- | 0.45+ or 0.44-} : or {0.445, |> 0.444444444445 |> 0.4 N4 +Decimal Places +5} Clipping operation depth of float; Is 3 operations or 2 with Stop count = 1 to 24 bit places + 1 or 2 for error rolling, up or down. Precision Clip Math OP | Clip > Cache {Math OP Use} Precision Counter Math OP + Counter(internal to FPU:CPU | Stop > Cache {Math OP Use} * Windows 3D Audio, DTS & Dolby Atmos should do to at least 32Bit 384Khz 7.1 Channels, There is absolutely no reason a 64Bit processor cannot do 64Bit audio, Mind you 32Bit Integer is around 60% of total CPU Support with 64Bit divided by 2, So 32Bit Audio is 100% speed conformant & there are few reasons to reduce it to 24Bit or 16Bit without processing benefaction; Such as Error management on 24Bit on 32Bit instruction: Both AMD & Intel X64 Rupert S 2022-11-30 "State-of-the-art approaches such as OpenMP and OpenCL"

[@and_I_am_Life_the_fixer_of_all]

its been 8 months, what are you views now?

[@DukeAbbaddon]

@@and_I_am_Life_the_fixer_of_all Very positive! Inference & FMA De-Block Styles For upscaling matrix: MMX+ & SiMD 16x16 Block as used just about in HD, 8x8 Blocks Certainly NTSC, PAL, JP_NTSC!, Very usable for deblocking JPG, 16x16 & 8x8 is very good for Inferencing active on Scaling & Deblocking.. 4x4 for main Inference XBox & 8x8 for PS5.. XBox can use (4x4)x4 for 8x8 & (4x4)x16 for 16x16; Very powerful! PS5 can use (8x8)x1 or x2 for 8x8 & (8x8)x4 (x8 for additional processing) for 16x16; Very powerful! Inference & FMA De-Block Styles List (4x4)x4 (4x4)x8 (4x4)x16 + processing (4x4)x32 +++ processing (8x8)x4 (8x8)x8 + processing (8x8)x16 + processing (16x16)x1 + processing (16x16)x2 ++ processing (16x16)x4 +++ processing 8:4Bit Concepts: 65535/255=8Bit 65535/16=4Bit 16bit/4bit : 4Bit colour pallet, But we can fraction 16Bit/4bit in essence 16/4! 65535/16; Compression Shapes & Gradients. Polygon, Shadow, Contact Alpha Channel 2Bit, 4Bit Grayscale edge define sharpening Single Colour Edge detect Shape Fill in Alpha 10,10,10,2 Xor, Pattern, Shading, Shader, Cull, Shape & Depth Compare after define