ARM Corelink, Arteris, UCIe, CXL and PCIe- Designing the interconnect is not for the weak-hearted!

This webinar presentation from Mirabilis Design focuses on system-level exploration and modeling of complex System-on-Chip (SoC) designs. It highlights the challenges in designing interconnects for high-performance SoCs, particularly when integrating multiple types of processors, memory, and communication interfaces. The presentation showcases VisualSim, a software platform that offers a comprehensive IP library for modeling different hardware components, including CPUs, GPUs, memories, and interconnects. It also emphasizes the importance of running simulations to explore different design options, evaluate performance, and optimize power consumption. The case study of a data center SoC and an automotive SoC demonstrates how VisualSim can be used to analyze and optimize the design for specific applications and requirements.
Suggested questions
How does VisualSim help engineers design and analyze the power consumption, performance, and functionality of complex SoCs?
What are the primary advantages of using VisualSim to model and simulate SoC architectures, especially for automotive and data center applications?
How does Mirabilis Design leverage AI and system-level modeling to accelerate the development process and improve the quality of SoC designs?
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