Arm vs RISC V- What You Need to Know

[@JB52520]

The whole point of RISC-V is that you _can_ make open source hardware using the RISC-V ISA without getting sued out of existence, not that you must, or that the processors don't cost money. The designs may be open and their users may have freedom. It enables open collaboration, reuse, and expansion within a well-defined instruction space designed to prevent collisions between predefined and custom extension sets. There could be a whole ecosystem of open designs just for pieces of cores, or software cores, FPGA cores, free implementations of custom extensions, or whatever people want to create and share. It's very much like Linux for hardware.

[@wertigon]

Indeed - while Gary is correct that someone still must build these designs, and building it especially large scale costs a lot of money, this cost can be greatly reduced by IP reuse. Software isn't exactly cheap to make either. Every CPU still needs an I/O die, and this is no different from every other I/O die on the market. Every CPU still needs a cache memory, FPU, and so on. These have existed for years, expired patents tell us how to build these already and as efficiently as possible. 90% of a CPU chip is the same components, so if these 90% were in the same standardized modular package that will eventually allow for lower costs. Think chiplets but at chip level. Think a CPU but sacrifice FPUs for hardware-accelerated packet switching. And so on. Lots of fun stuff that could be done here. :)

[@DragonsinGenesisPodcast]

Companies that design cores still patent those designs. While the architecture is open like Linux, the core designs and innovations that make those cores more useful and efficient can still be patented. And since the architecture is open, this will likely lead to multiple companies designing multiple cores using a variety of source codes that are controlled by different companies. This means that a unique innovation that could benefit all RISC V chips will only be available to whichever company designed it. So if one company designed a more efficient source code and another company designs a more powerful core, you can’t get a RISC V system that uses both the powerful core and efficient code because they’re property of two competing companies. This will lead to a fracturing of the technology with no single controlling all the best technologies. Instead the best innovations will be scattered among multiple designs, preventing any of them from reaching peak performance. This is not a limitation of ARM who can implement all innovations. This is why Intel is trying to buy up RISC V engineering companies, so they can control the best designs of these chips.

[@laharl2k]

if they would make an atmega pin compatible risc-V with faster speed and more memory it could really beat atmel on the arduino space in a second because even if its slow and obsolete many are still using it because thats what the arduinos come with and thats the platform the software was made on. It would be just a matter of making the chip and adding it to the arduino libraries. Just give me 300mhz and 4mb of ram and im sold.

[@devdylan6152]

@@laharl2k the new ESP32 C3 is using RISC-V

[@laharl2k]

@@devdylan6152 Make that into an arduino uno and arduino mega form factor and it will sell, otherwise we are still in the same situation where everything people use ws made for those so they keep using those instead, even if there are better alternatives.

[@youcantata]

I'd like to see more technical explanation on architectural difference between the two RISC architectures like register model, branch model, addressing mode, data/cache management, memory management, priority, interrupt, privilege, security model, vector mode etc. This video is just business introduction of two.

[@THB192]

There's not really as much to say there. AArch64 has some weird instructions RV64 doesn't, and some design differences, but it's not that crazy. RV32 vs 32-bit ARM is a bit more exciting because 32-bit ARM is extremely quirky.

[@reiniertl]

Well you have all the specifications out there. Is hard stuff to digest but cool if yo really like to understand computer architecture.

[@gast128]

Agree. I wonder how much the differences in ISA would contribute to differences in performance. Even the ancient x86 CISC instruction set has been accelerated under the hood by Intel's and AMD's trickery.

[@THB192]

@@gast128 The answer to that question is "it's complicated". Chris Celio did a talk on this while he was working in the BOOM RISC-V out of order core. Sort of on this, really. It was about stacking up ISAs and comparing them. Thing is, the ISA can impact how many instructions your program is, but it can't determine how fast they run. That's the province of the microarchitecture and the process. And if there is one thing x86 has proven it's that you can make almost any ISA run fast. However, an ISA can make a microarchitect's job easy or hard. x86 makes the microarchitect's job much much harder than it needs to be, and not really to any gain for programs: it's just that every x86 CPU needs to implement 50 years of legacy. RISC-V makes the microarchitect's job much easier, and the chip real estate you don't have to use on making x86 not terrible can be utilized in other ways. Of course, Intel and AMD still have some of the best microarchitects in the world, exceptional fab technology at their disposal, and enough guaranteed customers to bankroll the design, testing, and production of chips (and the upfront cost of producing chips, especially on the very small processes that Intel and AMD are using, is very high). That's why x86 is still beating everyone else's performance. Of course, none of this actually matters if your compiler sucks at utilizing your ISA, or you blow your instruction or data cache, or any number of other things. It turns out even if your program is CPU-bound the microarchitecture isn't always the bottleneck. My credentials on this subject are... zero. I don't have any. Don't trust me.

[@godnyx117]

@@THB192 More quirky than X86_X64?

[@fuseteam]

if you add 00:00 intro to your timecodes youtube will segment the video in chapters :3

[@thomasruwart1722]

I remember having the CISC vs RISC discussions in 1984 when I worked for a startup that was implementing a CPU using 6000-gate array logic from Control Data Corporation. We ended up implementing the MC68020 CISC instruction set in said gate arrays and it ran 10x the speed of the fastest 68020 chip at the time. But, as many startups of its time, it died in 2006 due to severe mismanagement at the top. Oh well, it was fun while it lasted.

[@spguy7559]

WoW . i'm from iran sir , is there any opportunity to understand RISC-V arch for me ? you swimming on the technology :) , if that's impossible we will find out the way from scratch . a nation under sanction can do anything finally .

[@derrheat154]

@@spguy7559 Hi, there is an online course from UC Berkeley called CS61C. They teach RISC-V but I dont know why you would need to learn it.

[@AnnatarTheMaia]

I'm going through teaching myself how to design circuits with the eventual goal of implementing my own MC68060-compatible core, not in design, but at an instruction level. Then after that, I'm going for synthesizing OpenSPARC T2 on an FPGA, with an eventual goal of building an OpenSPARC T2 1U 19" rack server. And then get the missing illumos support back in, which shouldn't be too difficult considering it comes from the SPARC platform. And then get SmartOS to build on it, once illumos support is upstreamed.

[@thomasruwart1722]

@@AnnatarTheMaia - That sounds like a fun project!

[@AnnatarTheMaia]

@@thomasruwart1722 I'm having so much fun learning how to design electronic circuits, I completely "found myself" in it.

[@paco3447]

One important thing to note is that ARM Vector extensions are actually SIMD (single instruction multiple data) despite the name, and RISC-V is not SIMD but real vector instructions by design (like old Cray-1 style vectorial machines).

[@u0000-u2x]

big deal for A.I.

[@BruceHoult]

ARM SVE is very similar to RISC-V V extension. Both are designed to deal with user vectors of any length (up to millions or billions of elements) using CPUs with vector registers of varying length (128 to 4096 bits for SVE, 32 to 2^32 bits for RISC-V) using exactly the same binary program instructions to give optimal results on any machine.

[@paco3447]

@@BruceHoult Sorry, but not at all. RISC-V RVV vector extensions when contrasted with ARM SVEx follows a profoundly different strategy. Another problem with ARM vs RV is that the former is simply large (+1000 vs a mere 48 ins in RV), RVV vector instr. fit on one single page and have a pretty simple syntax (ex. a simple vector load ins: VLD v0, x10). Yep, length is pretty similar, but ARM FP registers overlaps in the same register file/memory. RVV does not work like ARM, as long as holds in a separate register file, for example. ARM vector complexity is above RVV. And so on

[@BruceHoult]

@@paco3447 complexity is not a good thing in itself. Usability and effectiveness are just as important. I've been using real, production, RISC-V vector hardware (Alibaba C906 core) for several months now and it's very nice -- older 0.7.1 spec, but the differences between that and 1.0rc1 are trivial compared to the differences to SVE, let alone anything else.

[@paco3447]

@@BruceHoult Yep. But you now that both follows different strategies in many aspects of V instructions. For example, dealing with variable length vectors (more simpler in favour of RISC-V). Or vector register file partitioning. Yes, both have same amount of vect. regist. but R-V allows disable those regs and give it back to memory. Differences when calculating max vector length, etc. I'm not saying ARM is bad but both have quite different approaches and personally I believe RISC-V is more simpler than ARM.

[@daniahmed]

The professor has graced us again with some quality content.

[@nufosmatic]

From a compiler developer colleague - "RISC" stands for Real Important Stuff in Compilers...

[@randallcromer66]

I've always wanted to know the difference between the two and now I know. Thank you for sharing this cool information and video with us. You're really are one of the best KZbin channel's on here for everything about technology and for that I very much appreciate all you do to inform and educate us in this never ending change in technology. So please keep up the awesome work and I promise to keep coming back for more and sharing your video's with as many people as I possibly can because you definitely deserve it. 🤟🤓👍

[@esra_erimez]

This is the best treatment on the subject and its importance can't be over stated.

[@BruceHoult]

"Still waiting for a popular, prevalent RISC-V Arduino rival". Well, "popular" is up to buyers, but there are a large number of RISC-V boards in the Arduino space and have been for several years: 1) FE-310 based boards such as the HiFive1, HiFive1 rev b, LoFive R1, SparkFun RED-V RedBoard, SparkFun RED-V Thing Plus, 2) GD32VF103 boards such as the $4.90 Longan Nano, 3) K210 boards from $12.90 MAix BiT and $21 Maixduino. The K210 chip offers dual core 64 bit running at 400 MHz with 8 MB SRAM, plus a lot of peripherals such as ML accelerators. Really great value.

[@GaryExplains]

Popular is indeed up to the buyers that is the whole point. 🤦‍♂️

[@stevenmsaxe]

Remember the IBM 360? It was the first company to design an architecture, including the ISA, then create a family of mainframes that that ran it. They ranged from small, slow and cheap (Relatively), to big, fast and expensive. The purpose was any program written to the ISA, would run on any of the mainframes saving bunchers of money and development time, mainly for business computing. Later on, Fujitsu, Hitachi and Amdahl created mainframes that were cheaper and faster, running the same architecture. The goal was for a program to be written once, that could run on any compliant machine forever. So far, it has made billions for IBM, and saved Billions in reprogramming costs. It sounds like Risc-V is trying to to do the same thing. The market is very different today. ARM has achieved most of the success that IBM had, but a program written for an Iphone cannot run on an Adroid without change, because the architecture is different. If someone big settled on an architecture like..... - Risc-v - UEFI boot - POSIX Complient OS (Like Linux or BSD) Then we'd see the a huge adoption. The Holy Grail of computing is to write a program, and have it run everywhere without modification. Risc-v could be a big step toward that goal.

[@nufosmatic]

08:27 - I worked for a company that built a superminicomputer starting in about 1978 - Datacraft Slash 4 - 24 bits (twice as good as a PDP-8) 60us memory access - the 6024 architecture - and a memory-oriented RISC architecture with infinite indexing and hardware virtual memory. The good, old days of Silicon Beach aka Pompano Beach, Florida...

[@GegoXaren]

You forgot that EuroHPC is going to switch their cores from ARM to RISC-V for future designs. The compute module that they have designed are already RISC-V, but uses a an ARM cpu as an interface.

[@soraaoixxthebluesky]

We argue about ARM vs RISC-V. Now Prof gives us a new knowledge for us to learn. Lets go.

[@galdutro]

I have an impression that the RISC-V revolution is more akin to ANSI C than it is to Linux.

[@BruceHoult]

I'm thinking RISC-V is more like POSIX or the Single Unix Specification or something like that. Linux is just one "manufacturer" following this standard, with also the various *BSDs, Darwin, Windows with the appropriate subsystem, all the proprietary versions from Sun, HP, SGI etc. A mix of closed commercial and open source versions.

[@paulperkins1615]

@@BruceHoult If RISC-V is like POSIX, it is doomed to irrelevance. POSIX compliance looks like compatibility on paper, but that's all it's "good" for. To me it seems like an ISA is a language in which software is written, much as C is. An operating system is a different kind of beast.

[@worldhello1234]

@20:12 Yes, the Pinecil soldering iron from Pine64 features a RISC-V bumblebee microcontroller and is much more affordable than similar offerings with ARM microcontroller.

[@GaryExplains]

I think I said popular and prevalent.

[@tookitogo]

As if the MCU were responsible for the price difference! 🤣

[@jimgolab536]

Very well explained. Your point about the danger of an MMX effect is very apt and very concerning, especially as 1) it is intrinsic to RISC-V and 2) explicitly avoided by ARM (If I understood correctly).

[@jackmcmorrow]

Finally a clear comparison, I enjoyed it a lot!

[@melgross]

So, I read somewhere that Armv9 is to a large extent a back port of Apple’s additions to the current v8, with whatever ARM may have added and modified. Apple went to 64 bits only way back with the A7, they’re coming up on the A15 a bit later this year.

[@shadow7037932]

I think RISC will basically replace ARM for smaller MCUs/ARM cores like M0 as the extensions will allow someone like Ti to tailor and optimize their MCUs for very specific applications.

[@el-domo]

let me clearify something, for the ones who don't know about it: It is software in term of being a code, but it is not programming code. It is a description code (VHDL or Verilog) and when you write it you are not programming. You take this code and convert it do circuit and then to layout to make the hardware, or you use a FPGA as an example and "programm the hardware using the description code".

[@Ne0Freedom]

Open Source Software (OSS) has 3 types: 1» Open Source Applications 2» Open Source Operating Systems 3» Open Source Firmware When multiple people use a Secfification (eg API), that Specification becomes a Standard. Software that implements an Open Source API, can be closed source or open Source. RISC-V Firmware implements the RISC-V ISA Specification, Thus, RISC-V is Open Standard Hardware (OSH), similar to WiFi (IEEE 802.11), Ethernet (RJ-45), USB-C, etc. Comparing ARM to RISC-V, is like comparing Apples to Oranges. ARM vs Si-Five & Ali Baba T-Head would be good choice choices: ARM Licences ARM chip architectures to Samsung & Qualcomm. Si-Five Licences their version of RISC-V chip architectures to Framework. Ali Baba Lisences their version of RISC-V chip architectures to SiPEED & Milk-V.

[@gsQartman]

Great overview - as always, thank you for quality content!

[@jdh30]

"Raspberry Pi uses a 1.5GHz" Raspberry Pi 400 was released in 2020 and already ran at 1.8GHz. FWIW, Acer Spin 513 (Apr 2021) has a 2.1GHz Arm CPU and the Apple M1 in their Mac Books and Mac Mini currently runs at 3.2GHz and is due to be superceded next month. I looked at RISC V alternatives recently for fun and they're all dire in comparison. I'd guess 10x slower than the M1 and 10x more expensive than other Arm boards. In contrast, HiFive Unleashed to HiFive Unmatched took 2 years so I think they improving a lot slower as well. RISC V is an interesting idea but I'm not expecting any disruption here. Maybe the MCU market but RISC V prices are way too high to compete there.

[@user-fr3hy9uh6y]

I think we need to coin a new term. "Open National" Is the use of the processor controled by the US government. One of the selling points of the ARM is that it was not. Now with NIVIDA that may not be the case anymore. RISC V open iso may be the solution. Open National may give it the bost it needs to be the next standard.

[@catchnkill]

Complete misunderstanding. ARM does not manufacture chips. US government is putting the squeeze on manufacturing. No matter what instruction set you use what design your chip is on, they can ban you from manufacturing the chip.

[@michaelm1]

What about OpenPOWER? Isn't that RISC too? And "open"? With good performance? Though insane price.

[@tltaddme4824]

actually for Apple, if the RISC-V is better, they will do another transition. But for me, Apple invested in ARM for quite long and what they did to their chip is not based on what ARM designed, they designed themselves so it already work in the way Apple want.

[@abriotde]

What is fun is that 10 years ago, you could say the same about ARM and X86 (ARM could only run on Linux and Android) and maybe 20 years ago it was just on special embeded devices. And now ARM is on servers and at least Intel may died (we don't know of course). The change can be quick and with a free ISA and state who have politic interest to look for non-USA product it can be ever quicker.

[@OmDahake]

waiting for this kind for a long long time, finally found this, still not exactly what I wanted but still a good one

[@ContraVsGigi]

I am curious if the energy efficiency is similar between the RISC-V and the ARM one from a few years ago, the ones they said are comparable.

[@mikehosken4328]

“RISC architecture is going to change everything” Hackers 1995. I then went out and brought a PA-RISC based server and was blown away by the performance. Pity HP retired the arch. Still use PA-RISC based server to this day.

[@BlownMacTruck]

That quote was way outdated before that movie even came out. RISC had already changed the landscape significantly. Why would you use such a silly movie to make a serious quote? Why would that make you buy a PA machine? It’s not like they were useful for most people at the time, especially since you needed HP-UX to do anything useful (Lites wouldn’t show up until 96 and BSD after) - are you saying you had access to THAT too along with a dev toolchain?

[@mikehosken4328]

@@BlownMacTruck First server I brought in the early 2000s was an A180c that had HP-UX on it. I then installed Linux on it. Debian HPPA. Had that as my main email and web server till 2008 then went to an A500 and now using a RP3440. I’ve been helping with the port to this day. Still running the latest kernel etc. I like the fact that it’s not your standard architecture and sometimes you have to build your own security updates but it still does it’s work with less issues than the later AMD64 machines that I use. Hackers was a movie that got me and a lot of other people into more serious IT projects, it’s not the best movie out there but was good enough to make me interested.

[@madmotorcyclist]

You should do a youtube about LISP machines that were used to usher AI in during the 1980s-90s. It's sad such a powerful language didn't catch on.

[@candyemrys564]

I agree. I still use lisp. I like legacy systems.

[@murraymadness4674]

As one of three authors of multiple process lisp systems, I ported to 4 different multiple cpu machines, that cost $100,000+, and now a $5 PI has two, and $10 chips have 4, and we still can't program them effectively in parallel after 30 years. I am so tempted to bring back my NICL system, yet nobody would care.

[@madmotorcyclist]

@@murraymadness4674 I hear you. I did my initial work on Symbolics machines and finally ported over to Allegro Lisp on Sparcs.

[@AZOffRoadster]

@@madmotorcyclist At my last job we had Sparc Stations everywhere. My favorite part? The bios written in Forth.

[@pmarreck]

I remember visiting my CS212 prof for office hours in the early 90’s and spent the whole time asking him about his Symbolics workstation next to him that ran LISP natively

[@Gruggo]

After watching your video about Intel looking at RISC-V, I wanted to know how it differs to ARM but didn't find any vids or articles that outlined this specifically. And then this video shows up, thanks

[@Athiril]

The ESP32-C3 is RISC-V iirc. I’d say that would be an Arduino alternative

[@kibels894]

ESP32-C3 is out now and it's great, think you will see a plenty of Arduino-like designs based on it!

[@michaelrichter9427]

ARM chips are also found in a myriad of embedded systems, going the other direction.

[@davidhart1674]

Excellent explainer video! Gary I wonder if you can investigate and explain Apple's reportedly undocumented ARMv8 ISA extensions on the Apple M1 processor used to speed up x86 emulation.

[@destrierofdark_]

They implement the Intel memory model as a massive performance hack.

[@Bless3757]

yessss i'd love a video on this

[@davidhart1674]

@@destrierofdark_ does this mean that the Intel memory model when used executing x86-64 code works concurrently with the ARM load/store model when executing AArch64 code? Seems like a pretty sweet hack if they managed to do it with minimal silicon.

[@destrierofdark_]

@@davidhart1674 I'd imagine some very specific ASIC to convert it, or whatever the load/store of the ARM is doing is adapted to Intel. Either approach works, and the hack obviously performs amazing, and considering it's still that low of a wattage on the M1, that should tell you something.

[@mrjean9376]

I'm in love reading all of this technical discussion, thank you very much guys

[@mytechnotalent]

Brilliant as always Gary the most through comparison! Cheers!

[@rloadah]

Great observation on the difference between open source software and open source hardware!

[@GaryExplains]

Glad it was helpful!

[@F3ARNO3VIL]

I believe Si-Five Announced they're on P650 which is on the level of ARM Cortex-A77. Not bad IMO

[@GaryExplains]

Still 3 years behind. And it isn't in any actual products.

[@richardokeefe7410]

The BeagleV is now the VisionFive. Looking at the specs, and comparing it with the RPi 400 (which I have) drives home the fact that the ISA is not as important as it was. What counts is what is in the System-on-Chip. Graphics, vision processing, sound processing, neural net execution, deep learning, the CPU is only marginally involved in these. For many IoT applications, it's what the SoC offers here that will matter, not whether the CPU is ARM, x86, RISCV, or MIPS. RISCV enables *CPU* architecture research in a wonderful way. By the way, my RPi 400 came with the recommended power supply, but it doesn't have enough power on its USB ports to power any of the optical mice I have. I had to buy an extra powered USB hub.

[@TurboGoth]

One thing you might be interested in that involves RISC-V is its relevance in light of ARM's weirdness in China as of late. As of some UK policy to put a fork in ARM's doing business in China, whichever China company's ARM license went kaput and they've decided to go rogue in terms of licencing terms and agreements and are now just going full speed ahead without ARM's blessing. As you know, ARM is an IP company so cutting China off wasn't so simple as halting the export of physical chips. And now China is just doing what it wants. I had guessed they would have taken a more legitimate track or else take a RISC on trade agreements and so I had thought many Chinese manufacturers were gonna make a transition to RISC-V. Now, take note that the Android market is much of what these chips fuel and Android apps are portable Java (okay, technically, they are a custom Googlified form called Dalvrik apk's) but once Android itself was ported to RISC-V which was successfully done as of Jan 2021, then former ARM phones running Android could now run RISC-V instead.

[@seriouscat2231]

Well that's what the Chinese always do.

[@vslow4795]

Great video! I was delusional at multiple points, clarified for me!

[@JOGEZAI]

i am so glad that youtube suggested your channel❤

[@Andrew-rc3vh]

Espressif do a RISC-V processor: "ESP32-C3 is a single-core, 32-bit, RISC-V-based MCU with 400KB of SRAM, which is capable of running at 160MHz. It has integrated 2.4 GHz Wi-Fi". I've just looked up the price. It's 1.18 pounds for the entire computer module. The reason you do not want it to run at 1GHz is because it is wireless so you use it as a dumb terminal, and then you use the cloud to do the hard work if there is any to do. Good software helps tremendously. The wifi stack is done in hardware. It's rather amazing you can build an entire web server out of this and only consume about 100ma or so. The US is ripping you off!

[@law-abiding-criminal]

With all these added instructions over the years, can arm still be considered a RISC ISA?

[@jonwatte4293]

No.

[@bluesillybeard]

I'm not sure X86 has literally thounsands of pages of specification, tons and tons of seemingly useless bloated instructions, enormous amounts of legacy stuff, etc etc. ARM is still much simpler, being much less bloated, but it's still incredibly complicated. I think it's probably not such a RISC architecture anymore. I don't know the details of each processor, so I can't give you a properly educated answer.

[@xeridea]

From wiki "Most RISC architectures have fixed-length instructions (commonly 32 bits) and a simple encoding, which simplifies fetch, decode, and issue logic considerably." Basically, instructions are fixed length, significantly simplifying design, and thus increasing efficiency. Some instructions on CISC CPUs are multiple instructions on RISC CPUs, but the overall efficiency is much greater. CISC CPUs these days in practice take on this mentality. Instructions are broken up into smaller chunks, to allow higher clock speeds, and pipelined, multiple instructions being processed at once (not multicore, this is within the core), drawback of course is code branches, making accurate branch prediction extremely important. So RISC works on smaller instructions by design, CISC has complex instructions, and breaks them into smaller, wasting vast amounts of power with complex instruction decoding. Historically, CISC has had much higher single threaded performance, albeit at a higher power cost, but this gap is quickly narrowing, and where efficiency matters, reversed. Obviously in phones, efficiency is king, and with the M1, performance good enough for laptops.

[@jonwatte4293]

@@xeridea ... and in practice, ARM has thumb, RISC-V has RVC, and it's much more about how much an architecture can avoid or simplify complex architectural state in the speculation pipeline, than whether fetch/decode is complex. 30 years ago, fetch/decode complexity mattered, but not today. My question is: Does the approach in RISC-V pay off? What's the relative latency of a branch misprediction? How often does it run into a full pipeline flush? How much memory load pressure is avoided with the bigger register file? Those are differences that matter!

[@xeridea]

@@jonwatte4293 I am not an expert on the topic, I know there are obviously optimizations with the fetch decode, but in general x86 is far more complex, and less efficient. It has came a long way, and has been cool to see AMD come back, in a big way, now we have lots of cores, which is another way to gain efficiency, due to how energy use grows exponentially with voltage/frequency. Branch misprediction latency is heavily affected by the pipeline length. Full pipeline flush would be.... anytime there is a mispredicted branch. More registers don't lessen memory load, they allow more parallel operations with the instructions. Bigger cache reduces memory stress.

[@berndeckenfels]

Would be interesting to talk about european sovereignty plans in relation to RISC-V, if that helps here (also supply chain risks involved with the IP)

[@BeaglefreilaufKalkar]

Well, one thing,, Apples SoC are compliant to ARM, that doesnt mean that ARM compliant SoC are compliant to what Apple Makes. It only means that the ARM instruction sett will run on an Apple SoC, but the Apple SoC are very much more that just the ARM intstruction sett.

[@bkahlerventer]

The strength of Risc-V is the fact that it allows extensions. A company such as NVidia can now add an extension for GPU instructions. However getting this more expensive Cpu/Gpu to run on the base risc-v instructions implemented will be 100% possible. The cpu maker members that formed Risc-V International designed and ratified the standards to allow precisely this because of the restrictions from ARM.

[@RalphFreeman-ok5of]

At the microcontroller level the RISC-V based ESP32C3 and ESP32S3 are almost the same price , The C3 uses less power but is slower and a single core so I'm not sure if there would be any point in using the C3 with less features rather than the S3.... If I comes down to cost the RP2040 is probably the cheapest . .... Confused ?

[@mayurshah008]

Great one!!! Your videos are too much informative which no one else probably explain in the way you do it

[@GaryExplains]

I appreciate that!

[@primorock8141]

I like the way you explain everything, you've gained a new subscriber!

[@RichardZak]

Haiku supports (it’s working but rough around the edges) RISC-V, so there’s two OS options.

[@catchnkill]

Haiku is a small project with very slow progress. I installed the x86 version of Haiku beta under VMware months ago. Though it is a very old OS i.e. BeOS, it is surprisingly usable.

[@anythingbutASIC]

Gary explained a lot actually..

[@jackm819]

Gary please cover the differences between RISC-V, Intel itanium, POWER ISA (openpower)

[@GaryExplains]

That would be interesting for the real nerds, but since Itanium is basically died, I don't think it would be that interesting to a wider audience.

[@Teluric2]

Itanium use a very long word ops and risc is smaller , itanium is still used on Hp mainframes.

[@perforongo9078]

@@GaryExplains The issue would not be whether Itanium is interesting, but whether hearing about how Itanium works would be interesting. I think it is.

[@LordSoulSicarious]

Are designers required to publish documentation on custom RISC-V extensions? Not the implementations, but the actual instructions and what they do. Because it seems like that would help with the fragmentation problem, as that would mean that even if a big player gets involved and pushes through a bunch of tech requiring their own custom extensions, at least the other designers could do a clean room implementation of those same instructions to maintain cross-compatability.

[@crhu319]

the fact that it's NOT OPEN SOURCE HARDWARE is important. The hardware design can and usually does incorporate proprietary elements. It will take a lot of work to create a competitor to the ARM ISO based stack, and that work could be undertaken by a lot of conflicted parties (governments and militaries, huge foundry corporations). So it's actually SiFive that has a processor, just like ARM, that needs to be commercially licensed. Other companies can do this too based on RISC-V, so they're not starting from scratch, and the compilers would be targetting something very similar to SiFive's CPU, so it's harder to sustain a monopoly and that monopoly won't be on the instructions themselves. Source code can be completely closed, as long as the instruction set is implemented.

[@imranhq13]

arm is the most valuable company right now

[@billchatfield3064]

What about SPARC and PowerPC? They're RISC and have been around forever. Why can't we use them? Aren't they "open" also?

[@danielstromberg]

There may be a misunderstanding about the subtle difference between opensource and copyleft-licensed software. TTBOMK, all copyleft-licensed software is opensource, but not all opensource software is copyleft. Opensource is a broader, more encompassing term that includes things like BSD and MIT licenses that do not require you to distribute source code if you distribute binaries.

[@GaryExplains]

Indeed, the RISC-V ISA is free and open with a permissive license for use by anyone in all types of implementations. Designers are free to develop proprietary or open source implementations. Only the ISA is free and open, not the implementations.

[@ronch550]

I think a good next topic would be high density libraries. If you look at AMD's Zen cores you'll see that everything looks like mush. Very interesting. It's probably the one huge leap in recent years with regards to chip design.

[@abstractapproach634]

The big difference is that if you design a kick *ss ARM architecture, you have an entity that can pull the rug out from under you. (Like if you challenge Nvidia maybe) But if you prototype a kick *ss riscV chip, it's yours. You can share it if you want, sell it if you want, or both. That will encourage more architects to be drawn to it. So far we're talking very specific people with access power and skill set (that's the asterisk in riscV is open source*) but more of them can try, and that's good. Plus, with emulation, it may be possible that some sevant teenager from Nigeria uses riscV isa to make am amazing prototype plan, and that plan is his unless he chooses to forfeit control. Otherwise he could be strong strongARMed into giving up for pittens to the powers that be because he doesn't have the rights to use the ARM isa.

[@obstinatejack]

like how huawei was kicked out of the whole arm ecosystem

[@abstractapproach634]

@@obstinatejack I'll have to look that up. What comes to mind is the linux on mac project, maybe that's right but it may just be a similar name.

[@catchnkill]

@@obstinatejack not true. nothing like that. huawei can still use ARM instruction set. they cannot find companies to manufacture their ARM chips in advanced process technology only. in fact huawei will sell new phones early next year using Qualcomm SoCs. those Qualcomm SoCs are ARM chips

[@jason.doller]

Open Source does NOT mean you have to share any changes you make. Open source means that the source code or designs used to build the item are open to be viewed. There are open source licenses that require that changes be contributed back to the project, but there are also very popular and widely used open source licenses that do not require that changes be shared back. The GPL is an example of a license that requires giving code back. The MIT (and I believe BSD) licenses allow you to use open source code in a closed source project. The MPL (Mozilla Public License) allows you to use open source code in a closed source project, but requires that the MPL parts need to be published, RISC-V is indeed open source. It's just licensed under a permissive license that does not require giving back.

[@GaryExplains]

Thanks for the brief lesson on open source licenses 🤦‍♂️the point is that only the ISA is open, not the designs.

[@jason.doller]

​@@GaryExplains To clarify, the designs you refer to are the packaging of the processor (physical manufacturing) and the support hardware (motherboard, for lack of a better word). And you are correct inasmuch as the "designs" are not available as part of the open source RISC-V project, however, there are projects that are open source that do provide everything you need to create a working RISC-V processor. This obviously excludes everything else that goes into a SOC, but we are comparing two processor architectures, RISC-V to ARM, and while RISC-V certainly has closed source solutions, there are also purely open source solutions available too. I don't mean to be pedantic, but anyone who is interested in RISC-V Vs. Arm would need to understand that both open and closed solutions exist.

[@GaryExplains]

🤦‍♂️

[@fuseteam]

RISC V -> Berkley -> source code doesn't have to be released me: ah yes the BSD license

[@fuseteam]

@Coz Fi looks like someone didn't get the connection: - both RISC V and BSD originate at berkley - both RISC V and BSD don't require derivatives to release the source code

[@davidca96]

@@fuseteam I gotcha 😉

[@fuseteam]

@@davidca96 nice :3

[@jann5s___]

With all the current instruction features in armv9, can you still call it RISC?

[@tookitogo]

Indeed. In powerful processors, the RISC/CISC divide is really largely nonexistent, as RISC processors gained many more instructions, and CISC processors started breaking down “complex” instructions into simpler ones under the hood before sending them for execution.

[@ДмитрийБочарников-б1ь]

In my opinion, it has little sense to use buzz words like CISC and RISC in 2021. Modern ARMs and RISCs have very complex instruction sets. On the other hand, modern x86 CPUs have all attributes of RISC inside, i.e. load-store architecture, pipelines &c.

[@tookitogo]

Yes, exactly!!!!

[@ThomasGodart]

This video is pure gold. Thank you for sharing it 🙏

[@TurboGoth]

OMG THANK YOU for mentioning the BeagleV! I didn't know about it! But I've marked my calendar for next September! I can't wait!!! I already have a Beaglebone and having a RISC-V machine running Linux will be some real fun! I wonder if the mainstream WASM runners will implement machine translation for that architecture by then. I bet not!

[@GaryExplains]

It got cancelled.

[@TurboGoth]

Oh no!!! I'm rubbing all lamps looking for a genie to wish on now.

[@TurboGoth]

Furthermore, I've resolved to pull together some QEMU magic to get SOME OS running locally on RISC-V even if that OS is some minimal screen text loop. Oh hey! It looks like Debian has been ported to RISC-V. Here's hoping it can do with entirely virtualized devices. It might involve some annoying games but now i'm determined.

[@GaryExplains]

I have a video about emulating RISC-V on a Pi using qemu.

[@rosepark222]

ARM's been around decades and mere 6 years old SiFive is just 5 years behind ARM? I would be nervous if I were ARM.

[@EmmanuelGoldsteinUK]

I'd be interested in seeing a comparison of RV & MIPS, as I think that ARM has reached a point where it now competes directly in some spaces to x86, where as RV looks more comparable to where MIPS was a few years ago (in comparison to ARM as a competitor back then).

[@GaryExplains]

That would be interesting for the real nerds, but since MIPS basically died, I don't think it would be that interesting to a wider audience.

[@EmmanuelGoldsteinUK]

@@GaryExplains Yeah, I can understand that. I was just thinking that perhaps it would be a useful way to help predict if RV will become a direct competitor to ARM one day, or if they'll go the same way as MIPS as there just isn't the same degree of interest in RV. My instincts tell me that the industry usually works best when there are two major competitors in each space, and I think that for now x86 & ARM have all of the attention from big industry players and RV is just used by a few companies looking to explore, but without too much commitment from them and so will probably disappear before x86 dies off.

[@TorbjrnViemNess]

@@EmmanuelGoldsteinUK Fun fact: MIPS is now a RISC-V processor designer - www.eejournal.com/article/wait-what-mips-becomes-risc-v/

[@perforongo9078]

I actually think MIPS would be really interesting to hear about. MIPS powered the PS1, PS2, and Nintendo64. A lot of people alive played those consoles.

[@SchoolforHackers]

Prof. Gary keeps me in endless school.

[@lhorthy]

Please define your acronyms. What are ISA, ML, MTE, and DSP?

[@GaryExplains]

Sorry that you didn't know those particular ones. I am sure you can find them with just a minute or two on Google.

[@DavidStrube]

@@GaryExplains Surprisingly unhelpful response, Gary. You could've taken a moment to explain some of the more obscure parts of your explanation, but instead you chose to answer "Google it.". How very 27B/6 of you. Here, I'll take a stab: ISA: Instruction Set Architecture? (or International Society of Arboriculture) ML: Machine Learning? (or Multiple Lemurs) MTE: Multiple Terminal Emulator? (or Microsoft Technology Expert) DSP: Digital Signal Processor? (or Delaware State Police)

[@GaryExplains]

@@DavidStrube LOL. Well done for misunderstanding completely.

[@mark_5588]

In a future video would you consider commenting on the likelihood of any of these being offered retail and gaining motherboard support to become a 3rd choice in the home computer DIY to compete against the current Intel and AMD offerings? What about a chip and board combo like the RPi and others with Linux performance rivaling the current generation for people who don't game and therefore do not need to support massive and expensive GPUs?

[@alexanderwingeskog758]

My experience only... But ARM was a CPU, turned "Microcontroller", turned into a CPU/Powerful microcontroller, and then into a full blown "computer". Some people who design stuff still wanted a easy microcontroller for stuff. And I guess RISC-V could get back into that segment and then do a ARM transformation again to actually compete in the same market as ARM does today... with all the bells and whistles. I do know that you could still buy a really simple "ARM" compatible Micro controller type of chip ofc., But maybe for smaller company ARM might be a overkill and RISC-V might be more suitable?

[@TheJacklwilliams]

Got my subscription. Dude you are, wild. THANK YOU. GREAT PRESENTATION!

[@NanNaN-jw6hl]

T01:42 -- "A reduced instruction set RISC processor." Good. I need the reduced instruction set RISC processor to power my ATM teller machine, as I dispense redundant information in my capacity as the redundant information spreader, at the department of redundancy's redundancy of information department. Please read this message twice for full effect.

[@kayakMike1000]

You can implement the design in an fpga or emulator.

[@aliuzel4211]

An enthusiast can implement soft RISC-V on FPGA and customize according to their needs. What about ARM ?

[@GaryExplains]

True. Great for an enthusiast, but useless for anything practical. Also, there are plenty of soft CPUs out there.

[@aliuzel4211]

@@GaryExplains I don't agree with you. Developments on RISC-V denies what you have thoughts on RISC-V. My coin-sized 2,3cmx2,5cm FPGA test board will have 32-bit RISC-V, RAM, FLASH, MIPI DSI, MIPI CSI and be ready in mid December and I hope it will draw attention.

[@GaryExplains]

First kudos for developing that board. As an enthusiast project, that is great. But what does your coin-sized board give the world that we can't get already from the myriad of development boards that exist for ARM, ESP32, PIC, ATmega?

[@ricky865]

Are you going to do a ARM vs Power PC or X86 vs Power PC video someday .

[@GaryExplains]

That would be interesting, but I think that it is too niche and wouldn't be that popular.

[@abdullahmubarak6840]

Thanks for the explanation Gary! Appreciate it.

[@JelloPuddingMaster]

18:33 the point about EEE (embrace, extend, extinguish) is moot: the whole idea of the RISC-V project is to allow anyone to manufacture a chip with similar enough ISA to not have to re-engineer or relearn the wheel while allowing for cut down options for lower costs/power consumption. Even if someone like Microsoft made an extension for something like hashing or other cryptography and a lot of big companies use it it doesn't mean everyone has a use for it or that everyone _has_ to use it. Sure, Microsoft's proprietary bitcoin miner might not work on your RISC-V based processor because you didn't license their extension, but what does a pachinko machine have to do with that?

[@bonzo-er6ly]

Price/performace ratio remains critical to the success of either architecture. RISC-V has for sure the chance to surpass ARM because of its more modern basic design. But of course, somebody has to do it. Intel buying SiFive might be the critical mass to make that happen ...

[@ankiiths3274]

can you please . . . name some tech company ( small ones ) w.r.t RISC,X86 and ARM based . . . reckon to become . . . a big company in future . . . in terms of investments for today . . . in your opinion thank you

[@swarupkumar2]

Exactly the video I was looking for

[@RJLightning68]

Was the Acorn Archimedes ever sold in the USA???

[@AnnatarTheMaia]

I don't see a point of RISC-V when there are OpenSPARC T1 and T2, both licensed under the GPL.

[@ivanlaws622]

What are you talking about? The first prototype computer to use reduced instruction set computer (RISC) architecture was designed by IBM researcher John Cocke in 1970 David Patterson at Berkeley was the originator of the Berkeley RISC, and the RISC-V

[@ianboard544]

This was interesting, but I am trying to understand why, outside of novelty and not paying ARM royalties, would anyone using ARM processors consider RISC-V. I primarily develop for ARM Cortex M devices and there are some features I like - the trace and debug facilities and the interrupt controller - are there analogous features in RISC-V?

[@catchnkill]

RISC-V is instruction set stuff. The features available for a RISC-V depends on individual design. There are a few public domain design for RISC-V already. Some are university projects. Some are very simple MCUs.

[@ianboard544]

@@catchnkill I understand that, but I don't pick an MCU for the instruction set. I just want it to be easy to use, with good compiler support and things like the interrupt controller and debug support that just work. Don't get me wrong - I like the idea of RISC-V, I just don't see the compelling reason (yet) to switch to it. So far, all I see is if you make millions of something every year and don't want to pay ARM royalties.

[@jonathangerard745]

Was eagerly waiting for this video

[@THBek]

What about IBM Power processors, isn’t it a RISC architecture?

[@Teluric2]

Yes its like sparc and mips.

[@vincentvoillot6365]

Beside the ISA and the number of register, all CPU use the same generic unit ALU, MMU/AGU, FPU, etc... What's matter is the instruction per cycle and with there popularity X86 and ARM have highly optimise scheduler, branch prediction, cache logic and both use a superscalar dual-issue architecture at least. Last benchmark i saw from SiFive couldn't compete with a raspberry pico (cortex M0). Western Digital "claim" 2.9 mips per mhz for Swerv EH1, between a pentium pro (3mips/mhz) and an athlon (4 mips/mhz on FX) and in multicore it's around 2 mips/mhz/core. Looking for a RISC to replace an X86 ? you can shop on ebay for a old DEC Alpha AXP (RISC 64bit) like a EV7, excellent IPS for a 25 Years old CPU :D (X86 emulation in bios as fast as a pentium pro)

[@blakeliu3713]

So theoretically, a company can develop custom extensions+a compatible arch and license it to other company. The arch and custom extension is proprietary and if it gets widespread adoption, they could become the standard in the risc-v ecosystem. And eventually they could become another ARM.

[@jackgerberuae]

Yes, but it’s what they are trying to avoid, hence the ‘forking risk’ ….👀

[@TorbjrnViemNess]

Actually the PULP project (ETH Zürich and university of Bologna) has made a set of custom instructions that have become quite popular. They've released the specifications as a few custom extensions, and worked to get some of them into new standard extensions - kinda similar to upstreaming stuff to the Linux kernel. Then obviously no longer using the opcodes reserved for custom extensions but rather ones from the pool of standard reserved opcodes

[@1MarkKeller]

*GARY!!!* *Good Evening Professor!* *Good Evening Fellow Classmates!* stay safe out there everyone!

[@GaryExplains]

MARK!

[@KennethScharf]

People often focus on the size of the instruction set when comparing RISC and CISC, but that's not what's important. CISC based computers use a micro-sequencer running microcode to 'emulate' the exposed CISC instruction set. RISC based computers implement most, if not all of the exposed instruction set using hard wired logic. This means that RISC processors can run faster, getting more instructions per clock cycle than their CISC counterparts. However, many of today's CISC processors (such as X86-64) now have enough transistors on board to use RISC type implementation to get on parity with many RISC processors with clocks per instruction execution.

[@GaryExplains]

Indeed. Well said. I have a whole video covering that called CISC vs RISC.

[@tortysoft]

I was an Acorn guru... Archimedes was a tremendous computer. I wrote articles about it - sold in WH Smiths :-)

[@sgtnasty]

Didn't we go thru all this before with PowerPC? What is different now?

[@GaryExplains]

Exactly. I cover that in more detail in my videos about RISC-V.

[@cywestbrook7448]

Actually there is a sort of "RISC-V Arduino" - the ESP32-C2

[@GaryExplains]

AFAIK, There are several RISC-V microcontroller boards, some compatible with Arduino, but I said "popular and prevalent".

[@Pulsonar]

Slight confusion @ 15:00, about the difference between the RISCV hardware implementers - for example SiFive vs Western Digital? SiFive licenses their RISCV hardware implementation, but Western Digital doesn't, how does that workout for companies like Western Digital if other organisations can simply take Western Digitals RISCV core of the shelf for free?

[@GaryExplains]

That is a good question. I think the answer in the case of WD is that it doesn't care. It uses its RISC-V core internally (in the drive controller), it doesn't sell them as standalone things, and it doesn't lose any money if someone else does. So to make it look like an upstanding citizen of the open source community it can publish the design for its core and it costs WD nothing to do so.

[@Pulsonar]

@@GaryExplains ok, thanks for explaining so it doesn’t lose money. But couldn’t it boost revenue with a license model around its RISCV core IP like SiFive? Perhaps its pushing its reputation as an open source brand as you mentioned. Probably they are also monitoring to see if and how other companies use their unlicensed hardware for future business engagement that they can easily latch onto if it’s in a ‘hot’ industry application area that they hadn’t considered themselves.

[@fbifido2]

Has Microsoft made a Windows Core for RISC-V ??? or does WoA works out of the box ???

[@edgeeffect]

Is ARM really RISC anymore?.. I always feel that it kinda entered a grey area between RISC and CISC quite a long time ago now.

[@GaryExplains]

No, still very much RISC.