Auditing ZK circuits for a living (with David Wong - ZKSecurity.xyz)

[@slashbin_fr]

Awesome guy! Thk you

[@Rogisyl]

Great video!

[@alextrebek5237]

@36:10 @39:30 💯 this is in line with RISC vs CISC in terms of performance due to a reduced instruction set. General purpose cpus aren't specialized. So ASIC > FPGA (due to hw) > traditional CPU > VM. At some point we'd need either reduced instruction set VMs or reduced instruction set CPUs. The former is more likely, the latter would most likely be somewhat achieved via MLIR instead of new architecture. See the paper on using MLIR at the end of Moore's law