Automation and Other Languages

Presented at DVCon U.S. 2022
This video consists of 4 presentations.
1) Metadata Based Testbench Generation
1:25
By Daeseo Cha, Samsung Electronics
2) Automatic Translation of Natural Language to SystemVerilog Assertions
31:07
By Abhishek Chauhan, Agnisys Technology Pvt. Ltd.
3) A Comparative Study of CHISEL and SystemVerilog, Based on Logical Equivalent SweRV-EL2 RISC-V Core
1:00:00
By Junaid Ahmed, Lampro Mellon; Waleed Bin Ehsan, Lampro Mellon; Laraib Khan, Lampro Mellon; Asad Aleem, Lampro Mellon; Agha Ali Zeb, Lampro Mellon; Sarmad Paracha, Lampro Mellon; Abdul Hameed Akram, Lampro Mellon; Aashir Ahsan, Lampro Mellon
4) Flattening the UVM Learning Curve: Automated Solutions for DSP Filter Verification
1:30:21
By Avinash Lakshminarayana, Silicon Laboratories, Inc.; Eric Jackowski, Silicon Laboratories, Inc.; Eric Cigan, MathWorks; Mark Lin, MathWorks
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