C++20 on Xilinx FPGA with SYCL for Vitis - Ronan Keryell - CppCon 2021

cppcon.org/
github.com/Cpp...
---
FPGA (Field-Programmable Gate Arrays) are electronic devices which are programmable with a configuration memory to implement arbitrary electronic circuits. While they have been used for decades to implement various adaptable electronic components, they got some traction more recently to be used as generic programmable accelerators more suitable for software programmers.
There are already HLS (High-Level Synthesis) tools to translate some functions written with languages like C/C++ into equivalent electronic circuits which can be called from programs running on processors to accelerate parts of a global application, often in an energy-efficient way. The current limitation is that there are 2 different programs: the host part, running the main application, and the device part, glued together with an interface library without any type-safety guaranty.
Since the C++ standard does not address yet the concept of hardware heterogeneity and remote memory, the Khronos Group organization has developed SYCL, an open standard defining an executable DSL (Domain-Specific Language) using pure modern C++ without any extension. There are around 10 different SYCL implementations targeting various devices allowing a single-source C++ application to run on CPU and controlling various accelerators (CPU, GPU, DSP, AI...) in a unified way by using different backends at the same time in a single type-safe C++ program.
We present a SYCL implementation github.com/tri... targeting Xilinx Alveo FPGA cards by merging 2 different open-source implementations, Intel’s oneAPI DPC++ with some LLVM passes from triSYCL.
For a C++ audience, this presentation gives a concrete example on why the C++ standard does not describe detailed execution semantics (stack, cache, registers...): because C++ can be executed on devices which are not even processors.
While this presentation targets FPGA and a SYCL implementation from a specific vendor, the content provides also:
a generic introduction to FPGA which should be interesting outside of Xilinx or even without the use of SYCL;
how C++ can be translated in some equivalent electronic circuits;
a generic introduction to SYCL which should be interesting for people interested to know more about heterogeneous programming and C++, beyond only FPGA.
---
Ronan Keryell
Ronan Keryell is principal software engineer at Xilinx Research Labs, where he works on high-level programming models for heterogeneous systems, such as FPGA and CGRA, with the open-source github.com/tri... SYCL implementation.
He is the specification editor of the SYCL standard, member of the SYCL, SPIR & OpenCL standard committees from Khronos Group & ISO C++ committee.
Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science in 1992 from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer (a Jurassic GPU ancestor...) and its programming environment. He spent some time in the academia teaching and working on automatic parallelization, compilation of PGAS languages (High-Performance Fortran), high-level synthesis and co-design, networking and secure computing. He was co-founder of 3 start-ups, mainly in the area of High-Performance Computing, and was the technical lead of the Par4All automatic parallelizer at SILKAN, targeting OpenMP, CUDA & OpenCL from sequential C & Fortran. Before joining Xilinx, he worked at AMD on programming models for GPU.
---
Videos Filmed & Edited by Bash Films: www.BashFilms.com
KZbin Channel Managed by Digital Medium Ltd events.digital...
*--*

[@jhbonarius]

For me this is HLS all over again. Yes quick to get something running, but it generates logic which is very difficult to optimize or debug, as it's hard to trace back to the source. Especially a problem when it turns out there's a bug in the synthesis tool.. And you just never have the same control you have in HDL. Hard to be positive about this, sorry. I will look at it though.. And those Vivado visualizations features have been there for over 5 years?!

[@ronankeryell5234]

Yes you are right, since it uses HLS behind the scene it can not solves the problem of the existing tools. 😞But at least, it is more pleasant to do this with modern C++ than with older C++. 🙂But what is quite powerful with SYCL is that, since it is single-source C++, you have in the same program both the device part and the host part, so you have the type safety between the CPU and FPGA for free and you can write adaptable FPGA code which follows the use from the host code, enabling generic libraries.

[@bubble534]

I had no idea what SYCL was but I am currently writing C++17 on Xilinx FPGAs and this presentation definitely opened my eyes to this technology. If I understand it correctly, it allows us to directly synthesize the FPGA hardware designs from modern C++ code? If so, that's quite groundbreaking and a powerful engineering tool. As the previous comment mentioned, debugging could be an issue however.

[@jhbonarius]

You cannot use full C++. You have to write it in a specific way, with specific types and constructs. Don't expect you can just give it the Doom source code or such.

[@deathmaster4035]

Does this support lower end FPGAs like the Artix 7 (on the Basys 3 board) ?

[@shawnshaw9859]

does the FPGA logic contains some small CPU or DSP to run sycl kernel? or is it just a dumb hardware accelerator? in the latter case how can you run any 'kernel'

[@apenasmeucanal5984]

now that’s I title I couldn’t understand a single word