Cadence IC615 Virtuoso Tutorial 12: S-parameter analysis in Cadence ADEL

[@sumitaa223344]

this is awesome lecture for beginner level...

[@MudasirMir7]

Thanks for the appreciation! :)

[@ashishsontakke4040]

thank you sir.. very helpful.

[@vijendersharma100]

In NF (noise figure), you are selecting the wrong tab for step and stop value. Therefore, you are not getting any plot.

[@MudasirMir7]

Yes, I was in learning phase that time 😉

[@apsanakhatoon1565]

Sir, how can we add RF in , RF out pin in RF circuits

[@MudasirMir7]

You can use "port" from analogLib when you create the testbench of your circuit. If you are using Goldengate with cadence, there is option for RF pins directly.

[@AshwaniKumar-ou4pw]

,how to plot group delay vs frequency in cadence

[@MudasirMir7]

Following are the steps: 1. Do the ac simulation of your circuit. 2. Plot the output net magnitude (V) and then send it to the calculator. 3. There is a function "groupDelay" use that and you should get results . 4. Plot it and y-axis you see "seconds" unit and x- axis "Hz". that is your groupdelay Basically groupdelay is the derivative of phase w.r.t to frequency. There is another way to do it using S-parameter expression

[@AshwaniKumar-ou4pw]

@@MudasirMir7 thankyou for replying.I am currently pursuing Mtech from IIT kanpur, and since 10days I am trying to simulate the LNA power amplifier with lowest group delay over frequency range 3.1ghz to 10.6ghz . I have few questions,the IEEE paper which I am trying to simulate has taken Vin to be 2.5V but in UMC 180nm CMOS max we can take maximum 1.8v na??? Second question is that how much variation can be in the result of group delay,power ,S Parameter,Ac gain if Vin is taken to be 1.8v instead of 2.5v ? And one request is that please tell how that other way of getting group delay vs frequency using S parameter

[@MudasirMir7]

You are welcome! >> They have used the I/O devices of 180 nm (VDD=2.5V). It is an old trick to achieve better performances, mostly linearity. Therefore when you scale down and using core device in 180 nm, the VDD as well as i/p signal will scale down(VDD=1.8V). >> For sure you won't be able to match their results (linearity, gain, NF) but with FoM you should justify that your results are competitive enough. You are targeting a wide-band so good luck! :). Moreover do MC of these parameters for more understanding. >> I don't remember the formulla (using groupdelay was convinent for me). Look in application notes of keysight ADS.

[@asthn1]

"S-parameters" Noise Figure and "Noise" Noise Figure what is the difference ?I so confused

[@MrViju13]

Why you took 1K ohm resistor at the output.

[@MudasirMir7]

The intention of these tutorials is just to explain the procedure for doing different simulations. So I took an arbitrary load