Carry Propagation Delay in Ripple Carry Adder || Lesson 86 || Digital Electronics || Learning Monkey

[@adarshbalachandar8680]

Wow! your lectures on DIGITAL Logic are good! Keep it up!

[@4ed747]

Watch the previous videos to understand Ripple Carry Adder. This lecture starts at 1:03. All the best.

[@AnkitKumar-nn8ni]

Nice explanation sir

[@Ankit-yv8tz]

If each full adder stage has a propagation delay of 20 nanoseconds, then S3 will reach its final correct value after 60 (20 × 3) nanoseconds. Is it correct for 4 bit number?

[@guttaumasankar8909]

Actually we assumed 2sec for each gate level.... We have 2 gate levels in each of circuits for Sum & Carry so total delay for 1 FA is 8 sec..... Right ....????

[@guttaumasankar8909]

But U have taken only 4sec delay for 1 FA circuit consisting both Sum and Carry circuit........???🤔🤔🤔

[@sushmanaik2228]

For two gate levels delay is 4 seconds..Sum and carry generated at end of second gate level at a time.. so 4 seconds is considered

[@satishpampanaboina2409]

Sir, Disign of QSD multiplier using HDL. Concept tell me a vedeo

[@Hans-tr6dx]

I don't like the intro. The rest is good though. Thanks