Circuit Board Layout for EMC: Example 3

This printed circuit board does not meet the FCC Class B radiated EMI requirements. In this example we'll redesign this layout so that radiated and conducted emissions requirements are easily met. We'll also improve immunity to radiated and conducted interference.

[@Uko_]

Would you mind to make a fourth example video where splitting the ground planes is necessary and explaining it in depth?

[@RandyLott]

There are many occasions where the board designer does not have any control over mechanical design, including connector locations. I suppose the only thing you can do is to control the loop area and do your best with placement. This is a very good series of videos! Thank you!

[@LearnEMC]

Thank you for your comment. Yes, sometimes we are forced to located high-speed circuitry between connectors. We can control transition times and loop areas, but if we have 10s of milliamps at 10s of MHz returning in the ground plane, we will probably require a metal enclosure or a ground structure off the board that we can connect our cable shields to.

[@stevehunt2125]

Excellent series. Thanks :)

[@seshansesha7645]

Very useful, Thank you

[@pengon13]

It is good for me

[@akhil3rockstar]

The split in ground will reduce the common mode signal to the connector. There should be a group split. The ic is a high speed digital circuit then high harmonic return signal may go through the connector shield this causes cm radiation. Use feriite beads to isolate the gnd planes.

[@LearnEMC]

The high-frequency currents will return beneath their respective traces. They will not venture out onto a cable shield unless there is a voltage driving them in that direction. The voltage across the gap is exactly the type of voltage that will drive currents onto the cable shield. We NEVER use gaps in a plane to control the flow of high-frequency current.

[@akhil3rockstar]

@@LearnEMC if the shield may act like an antenna then common mode signal will radiates out. in the book by Bruce Archambeault page 112 , he provided some measurement of split and without split. Ther is around 10 dB difference for the results

[@LearnEMC]

@@akhil3rockstar Thanks for pointing to a specific example! The example you are referring to describes shielded enclosure resonances coupling to an external cable. In that example, the split interferes with the coupling at the lowest enclosure resonances. It is very different from this case where we do not have an enclosure. It is also important to note that the book you mentioned was published 18 years ago. If you've seen any of Dr. Archambeault's presentations recently, he always has illustrations and simulation results showing that high-frequency currents are largely confined to the area of the return plane directly under the trace, and he does not recommend splitting ground planes to control the flow of high-frequency currents.

[@PyroShim]

Very helpful examples! Are there any further examples planned?

[@aymanjundi7540]

(min 20:52) in your modified design, the second (lower) chip has it's connection to the DAC traced to another pin on the same chip that wasn't there in the original design, is that a simple drawing mistake? The shunt caps due to transients, isn't that going to mismatch impedances on those RF lines? considering the fact that they go from tens to hundreds of MHz, does it need a re-matching network to compensate for this cap? In the end, i can't thank you enough, very educational content, Example 2 helped me solving AND understanding an issue i had with split grounds, now i know better.

[@LearnEMC]

Thank you for the comments. The black traces are not on the top layer. The shunt capacitors must have a value that passes the desired RF signal, while shunting higher frequencies. The point is to allow some control of the frequencies coming in and going out of the board.

[@seanm8030]

? This stackup will not work.

[@LearnEMC]

In this application, it works well. For a given design there can be good or bad layer stack-ups, but the best layer stack-up will always depend on the application.

[@mikal_1]

What about the most important thing (or one of the most important), board stackup? that six layer stackup is just god awful for reduced EMI. Signals on layer 1 have to travel through one other signal plane before getting to the ground and power planes. In higher speeds than this (or higher rise times than 1 ns) this board stackup would not pass the EMI test. Go watch Rick Hartley and read his stuff

[@LearnEMC]

It is absolutely incorrect to suggest that this stack-up is "god awful." I have had this conversation with Mr. Hartley. He and I agree that the best stack-up will depend on the application. It is entirely possible to build boards that have signals with fast transitions and only two (of six) solid planes. You just need to follow the currents. In fact, at the time this video was made (in 2015) we were guaranteeing the EMC compliance of designs like this and never had one fail. Nevertheless, I would agree that 6-Layer designs with large numbers of Gbps nets will require more than one ground plane and that one of those ground planes will be on Layer 2 or 5. Be careful about applying design rules (e.g. recommended stack-ups) blindly. Adding extra layers to a board design is a significant cost hit (at least in automotive or consumer electronics). Do it when you know it's necessary, not just to comply with a design guideline.

[@enthusiastictube]

@@LearnEMC I think that the stack up suggested would work as long as layer 1 and 2 are routed with perpendicular directions as it used to be the practice. For instance layer 1 only horizontal tracks and layer 2 vertical tracks. Otherwise I would imagine there will be a significant crosstalk between these layers as they both share layer 3 for reference. Personally I follow Mr. Hartley's recommendations regarding stack up. Anyway, great video! I just ordered the book to get access to the rest! Thanks