Clock Skew in VLSI | Positive Skew | Negative Skew | Global Skew | Local Skew

[@suprajithhs5609]

Once again an excellent video. The answer to your in video question, Which type of skew is helpful for setup and hold fixing ? : Positive skew is good for fixing setup time violations where as negative skew is good for hold time violations. Positive skew can be seen as widening of the window in which the data needs to get stabilized before the arrival of the capture clock. But this is bad for your hold time requirements. Similarly, we can infer the case with negative skew being good for ensuring hold time requirements, but it being bad for setup time requirements. Please let me know your answer.

[@TeamVLSI]

Thanks Suprajith, Excellent!!!

[@gittollahussain3872]

Positive skew is helpful for setup and negative skew is helpful for hold. Why because positive skew is nothing but capture clock latency is greater than launch clock latency.capture clock is more

[@TeamVLSI]

Hi Gittolla, You are right.

[@padmajmanore8886]

Hello SIr, I think so negative skew is not going to help to resolve the hold violation. I'm saying this because our hold time of the D f/f is fixed (Inverter delay) so even though if our Tclk is reducing, it is not gonna create any impact on the hold violation. That is my thinking. Please correct me if I'm wrong. Thank you so much

[@deepakbabu720]

can you make a video on clock exceptions in cts

[@ajaythedarling]

@Team VLSI Thanks for sharing info, can you help us with the reasoning for the question There is 2 cases 1) 800 ps Latency and 50 ps Skew 2) 400 ps Latency and 120 ps Skew what's the difference and the results expected in a R2R path

[@anita_sharma3232]

Very good video

[@TeamVLSI]

Thanks a lot Anita.

[@vijaysagarbablu]

Positive skew helpful to fix setup and negative skew helpful to fix hold timing violations.

[@TeamVLSI]

Right Vijay.

[@atuntripathy]

@@TeamVLSI Sir Ji, This is not a correct concept. If I see negative skew , I would be worried that there is something wrong in my clock tree and debug and fix it. You just imagine that the clock is reaching capture flop before even data is launched. I would freak out with this. How can this help hold? First of all this should not happen like this. Practically negative skew represents- something wrong in your clock tree , go and debug.

[@dowlurijagadeesh5921]

@@atuntripathy yes u r correct , but mathematically it will help to fix the hold violation

[@georgehovhannisyan5003]

excellent video thank you please make video about arrival time and required time

[@TeamVLSI]

Sure @George.

[@georgehovhannisyan5003]

@@TeamVLSI thank you

[@jagruthgowda3006]

Nice class sir I have a question Consider we have two flipflops (ff1 and ff2)and data transmission is happening from ff1 to ff2 but these two fliflops are getting two different clock signal of same time period ( clk1=clk2=4ns) 1.Does STA tool report this path ? 2.Is this path Synchronous or Asynchronous path ? 3.If in case it is synchronous path can we able to report the skew between these two paths?

[@TeamVLSI]

Thanks jagruth, Here is the answer of your questions. 1. Yes, STA Tool will report the timing path. 2. Can't say anything unless you tell the about the phase relationship between clk1 and clk2. Point is, if there is a integral multiple of frequency and a constant or Zero phase difference, it will be a synchronous path and if there is no definite frequency and phase relationship, it will be considered as asynchronous path. 3. Yes we can.

[@jagruthgowda3006]

Thank you sir.... To report the skew between these type of path do we need to mention any exceptions while doing CTS

[@gittollahussain3872]

Frequency is didn't decide the this is synchronous or asynchronous.it will be dicide the based on the those clock is coming from same source Or not. If those two clocks are coming from same source that is synchronous other wise asynchronous

[@radhaa6564]

@@gittollahussain3872 yes You are right sir

[@merrygo7189]

Which is good b/w these two conditions 1..150 ps latency and 30 ps skew 2.. 100 ps latency and 50 ps skew

[@TeamVLSI]

2nd case

[@merrygo7189]

Can you explain how

[@paraprannoy3732]

@@TeamVLSI How sir? and btw thanks for making out these videos sir.

[@srinulucky743]

If skew is zero what will happens and it is possible Or not?

[@TeamVLSI]

Hi Srinu, Zero skew is not good for power prospective. It would demand high switching power at once and so rush current as well.

[@srinulucky743]

@@TeamVLSI thank you

[@kenishastills-ogburn4197]

Would it possible to get a visual for how the a positive and negative skew affect the setup and hold time windows?

[@TeamVLSI]

Hi Kenisha, Not visual but we can calculate it very easily.

[@raveenasaldana3143]

What is abnormal skew. ?

[@TeamVLSI]

Hi Raveena, Have I used this terminology? If so please mention the time stamp.

[@Superman-end]

how can you take the expected skew

[@TeamVLSI]

Hi Kalla, It depends, Like based on slack we can do skewing.