CMOS COMBINATIONAL LOGIC DESIGN

[@bhavanasure1145]

Damnnn...you're really a gem sir, explained in a very simple way. Thanks a lot sir

[@profbarapatestutorials]

You are most welcome

[@arnavkowadkar1497]

Sir your Pull Up Network is wrong, as for PMOS (A.B) should be parallel with (C+D), because they are ANDed [(A.B) AND (C+D)]

[@Syoutubes3974]

Yes I also think ,it should be in parallel

[@garde8072]

I also agree with this

[@N__HarshadaKharat]

Thank you so much sir 🙏🏻🙌🏻

[@AyeshaInamdar-v2u]

Thanks alot sir 🙏 👍

[@profbarapatestutorials]

Most welcome

[@profbarapatestutorials]

Most welcome

[@garde8072]

❤❤