CombCkt - 4 - Logic Gate Capacitance

[@skn3789]

23:07 The diffusion of the pmos can still be shared although it's contacted so total should be 4C?

[@ofek2852]

He explicitly noted that it is because of the contact metal, one should ensure enough space to meet DRC. Therefore, it is considered as separated capacitance

[@fakeraees5790]

This topic is very confusing. At 8:00 Where Cgsp, Cgsn gone??

[@socialogic9777]

Cgbn - capacitance between gate and body contributes to net drain capacitance or net gate capacitance? Similarly Cgbp in PMOS case?

[@AbhishekSingh-up4rv]

net gate capacitance is sum of (Cgb + Cdgd+ Cgs)nmos = C

[@bharadwaj767]

10::45_16-04-24_@IIIT-H In Nand, N1 drain and N2 source shares same diffusion (so, single cap C) But P1 & P2 drains could also be considered as common diffusion right!? --> we have metal contact thus we need a finite spacing b/w both P1, P2 drains diffusions (I don't understand this)

[@ofek2852]

This spacing results a separated capacitance

[@joyatidas1016]

is the layout of the NAND gate correct? Won't the position of A and B gates reversed.

[@chetanggs]

Position of A and B connection doesnot matter , As at the end Y=(AB)'

[@pseudohawk1656]

Can we share diffusion cap of transistors who have different widths?

[@pseudohawk1656]

Like 2 in series with 4 sized NMOS

[@ofek2852]

No you can't. It is not considered as shared because different width results in different capacitance by definition. Moreover, I don't think we use different sizes of transistors at the same design\process. Instead, one can connect a bunch of transistors in series\parallel

[@vivekkar7921]

what is effect of gate capacitance on leakage current

[@ofek2852]

If you're asking about leakage current, it means you are analyzing your circuit in dc. hence you shouldn't care about your parasitic capacitance. btw, leakage is at OFF state where delay consequences are not relevant. Therefore, parasitic caps are not relevant.