CppCon 2018: Olivier Giroux “High-Radix Concurrent C++”

CppCon.org
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Presentation Slides, PDFs, Source Code and other presenter materials are available at: github.com/Cpp...
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In this talk we will share the joy of seeing ordinary C++ concurrent code, doing ordinary concurrent things in 100000 concurrent threads. I’ll analyze how the code is behaving and point out what is similar and different about the execution of that code at this scale. This talk is the code-heavy continuation of last year’s English-heavy “Designing C++ Hardware” about the Volta architecture.
Featuring:
Multiple compilers.
Godbolting.
C++20 concurrency predictions.
Live demo (attempt).
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Olivier Giroux, NVIDIA
Distinguished Architect
Olivier Giroux has worked on nine GPU and five SM architecture generations released by NVIDIA. Lately, he works to clarify the forms and semantics of valid GPU programs, present and future. He was the programming model lead for the NVIDIA Volta architecture. He is the chair of SG1, the Concurrency study group of the ISO C++ committee, and is a passionate contributor to C++'s forward progress guarantees and memory model.
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Videos Filmed & Edited by Bash Films: www.BashFilms.com *-----*
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[@piotrarturklos]

This video contains a crash course on CUDA, as well as a great explanation of what CUDA is and what is it capable of.

[@krytharn]

Awesome presentation, well prepared and very interesting.

[@OperationDarkside]

What a surprising change from heavy french accent to barely noticable

[@zhaoli2984]

impressive talk, thank you.

[@nteasushz]

Great video. Thanks for sharing.

[@llothar68]

9min into and upvoted. Finally a very interesting topic for me. ..... Later: still nice but unfortunately we have to wait until this hardware becomes mainstream and we can use it in our programs. Lucky are the server side programmers :-(

[@BillyONeal]

If your algorithm is wait free it works on older GPUs too.

[@OperationDarkside]

Will there be a re-upload? Because the microphons seemed to be off.

[@piotrarturklos]

The microphones are only off for the questions. Furthermore, if you are in a quiet room, you can hear the questions anyway.

[@TruthNerds]

I didn't even watch the whole talk TBH, but 7:28 triggered me[1]… a trie is *not* characterized by a "large fanout". Many tries have a (potentially) large fanout, but binary tries are perfectly possible, and occasionally very useful, particularly for CIDR[2], even though actual hardware routers on the Internet usually use TCAM[3] instead. [1] www.xkcd.com/386 [2] de.wikipedia.org/wiki/Classless_Inter-Domain_Routing [3] en.wikipedia.org/wiki/Content-addressable_memory#Ternary_CAMs

[@the1969huff]

*its title

[@Voy2378]

I get that this guy works for nV but it is really deceptive what he did with CPU... nobody would write such dumb code for CPU. If you wanted to really parallelize code on CPU you would have 1 triee per CPU core and partition words based on first letter(or something smarter to each CPU).... way he wrote it contention is horrific.

[@catlakprofesormfb]

But it is the same for the gpu code

[@BillyONeal]

Fan out here is like 26x, that’s the high radix part. Actual contention is very low.

[@Voy2378]

@@BillyONeal If only there was this thing called false sharing...

[@Voy2378]

@@BillyONeal also he probably uses the same allocator for all 40 cores... lol

[@BillyONeal]

Voy2378 these things are way bigger than cache lines so false sharing isn’t really an issue.