CPU bus in FPGA programming

[@StatusFIX]

it may seem silly , but i have been trying to understand term which is used all the time in many of the books i have , the logic high or low 0 etc , and with that small example has just helped me understand that little bit more.

[@m1geo]

Useful, thanks! 👏

[@travelthetropics6190]

I was going through a FPGA PC project and found that it is using "Wishbone" bus to connect Softcore to other components? Do you know a way to extend "Wishbone" bus to a physical CPU ? Any idea would be appreciated.

[@CompuSAR]

I'm not particularly versed in Wishbone, but it should be possible (assuming the CPU you want to connect to has a Wishbone interface, that is). The bus was designed to be extensible, so exporting it to the FPGA pins should be possible. Of course, that leads you to the world of hurt that is timing requirement, electromagnetic interference and clocks.

[@samborms]

A good video

[@CompuSAR]

Thank you.

[@samborms]

​@@CompuSAR it's an interesting way to apply the concept, I know there are a series of videos about this project, but maybe some people would find enjoyable get down more deep in than original proposal, and I know there is a series of videos about inside a CPU, but is better to use a well know IC as base

[@CompuSAR]

@@samborms I'm sorry, I don't understand your proposal.

[@samborms]

@@CompuSAR my apology, I couldn't explain myself right. I mean: "There is many videos about make a computer using a 8 bit microprocessor, but this is the first time I see the implementation of the architecture of one those 8 bit microprocessor using a FPGA", this is a one l more down level in the design of a 8 bit computer, good job.

[@CompuSAR]

@@samborms Again, thank you.