D-type flip flop timing diagram explained | EDUQAS GCSE Electronics

[@littlebossy.]

YOU ARE A LIFE SAVER... i just came across this vid. I have my test tomorrow and i was LITERALLY crying..... I dont know how manyyyyy vids i have seen for this d flip flop timing graph... thanksss. ur video make sense to me :)

[@ea1766]

This concept made no sense till i came across this video, even in a level this is extremely useful, thanks!

[@PizzeyTechnology]

Glad it was helpful!

[@lazuardirinaldi7516]

Simple and straightforward. Thanks!

[@zakm]

I did a question similar to this and had no idea how to answer it because the mark scheme didn't tell me anything. You have helped me lots for my electronics exam tomorrow, thank you!

[@PizzeyTechnology]

Glad it helped!

[@mrkhaled5075]

you saved my life man, thanks

[@PizzeyTechnology]

Glad to hear it helped. Don't forget to subscribe. 😀

[@omerayad8742]

man you are awesome thank you a lot

[@kipbowen974]

Excellent

[@captaincrunchcam5478]

Thank you! I couldnt figure out how to draw the diagram with out drawing the output of the first dlatch that feeds into the second dlatch to see what data is being held by the first one

[@neymar8714]

What will the timing diagram look like if we had Q' as the clock for the next Sr flip flop

[@snkrsbysam2045]

you're the goat

[@charliecvitkovich7694]

thank you!

[@stefanosignorelli3666]

Thank you!

[@shy4real]

made me understand more than my 2 hour lecture 🤦🏻‍♂️

[@Bazouun]

i like

[@jimmygore8214]

Thanks

[@_interesting_clips_]

Love you ❤️