Designing an 8-bit CPU - 1 - project goals

[@weirdboyjim]

"And then life happened". Doesn't it always!

[@phodopus42]

And never little by little - everything happens at once! 😅

[@PhilBoswell]

I looked at your 65816 project but the playlist is all messed up so I'm starting here instead!

[@phodopus42]

Oops, yes it in the wrong order. Thanks for noticing and letting me know 🙂

[@cthutu]

Use Obsidian or something similar to keep a journal on your work as you do it. You can add images, mermaid graphs and text to document your travels. If you have to take a break due to real life, hopefully your notes are enough to get you back into the swing of things. Take particular note of problems and their solutions you come across.

[@phodopus42]

Thanks for the recommendation 👍 I've not seen Obsidian before. I'm pretty old school in that I use a notebook and a pencil. Whenever I have an idea, I write it down, even if I just cross it out moments later. I was a bit shocked to find a 15 day gap between entries recently 😥 Work has been absorbing all my energy recently because we have a looming deadline.

[@MattSiegel]

appreciate the thorough analysis and clear explanation :D

[@phodopus42]

Thank you! All these ideas float around my head, and I find explaining it crystallizes them 😀

[@cthutu]

I hit the same issues when designing my 6502-inspired CPU (I plan to implement on an FPGA). However, I do like you 2-register ALU approach. Even though it uses 4 instructions, I could see assembler support for pseudo instructions that use A0 and A1. I am wondering, therefore, if a 16-bit ISA would be more useful.

[@phodopus42]

So... OK... this got me thinking. Since the start, I've been jumping back and forth between the idea of this ALU register. I never liked it. I ended up settling on a 2-byte opcode for ALU ops to avoid it. I was walking through the pipeline stages for instructions. Loads & stores take minimum 2 cycles (fetch opcode, perform load/store), or 3 cycles if there's an immediate (fetch opcode, fetch offset, perform load/store). ALU ops take 2 cycles because it's a giant opcode. OK, so what instructions only take 1 cycle? Virtually none. And I believe you are completely right. I sketched out the opcodes assuming they are all 2-bytes, and suddenly there is room to breathe! Let me play through the scenarios and I may have an update in the next video. Thank you for a provocative and helpful suggestion 👍 I'd love to see your FPGA design.

[@BlueChrome]

You also have the option of going the 68000 route with regard to registers and splitting the register file in two, one half a set data registers and the other half a set of address registers. So only two bits needed to specify a register - with the type of instruction being executed deciding which half of the register file is to be addressed by the hardware.

[@phodopus42]

I didn't realise the 68k did that. I grew up on the 6502, a tiny bit of Z80, then ARM, then joined the masses with x86 (although the only serious assembly I've done in x86 was for hand-optimising SIMD 🤯). It's a neat idea, for sure. I kinda wanted a "RISC-like" architecture in that all registers are treated equal. I guess I have a soft spot for ARM 😆 I have more ideas... too many ideas to implement. Thanks for watching & commenting 👍

[@BlueChrome]

​@@phodopus42 > Well with sixteen odd registers to deal with, and the division was not done as strictly as I make out, but we're talking about a sixteen bit instruction (minimally, they can get much bigger) versus your eight bit. But still interesting to see what you end up going with.

[@ruslanzalata]

I think, you better start with data path design, instruction set will depend on what DP you could do. Second, you do not need so many ALU ops. You need AND, OR, XOR, ADD, SUB, SLL, SLR, i.e. 3 bits. Also, why so many regs ? Go the 6502 route - A, B, H, L. Use H and L for memory access. 8 bits is plenty of space for encoding instructions. :)

[@phodopus42]

Thanks :) I wanted something more "RISC-like" so that I can avoid complex instructions like the 6502's indirect memory accesses. That's why I ended up with 8 registers. I'm currently designing the data paths and decoder. In retrospect, that's where I should have started. As I've probably pointed out, I'm not an expert here! I am reconsidering the whole instruction set as a consequence. I've been programming some simulators at different levels: a high-level one for the instruction set, and a lower-level one simulating the data paths and control logic. This gives me the advantage that I can try something out without hours of work on the breadboards.

[@DirkJMartens]

What happened to the VGA card?

[@phodopus42]

It's still in a drawer :) I will do a wrap-up video to finish the series.