Double pulse testing: assessing switching performance in power MOSFET applications

[@akashtarwade]

Nice explanation, I just want to know, how much does Low side Vds, drops at gate turn_on. Reason behind more drop below at the turn_on instance.

[@Nexperia]

Hi @akashtarwade5460 , thanks for the question. Our engineer answered - Please have a look at the Application Note 90011, mainly at figures 5 and 10, and their explanations: assets.nexperia.com/documents/application-note/AN90011.pdf The drop occurs mainly due to parasitic inductance in the circuit and high di/dt.

[@LEO22116]

Thank you for your video. I have two questions if you do not mind: 1) How does the inductor size effect the results? I think it should be chosen around the same size as will be in the application. 2) Is measuring the stray inductance possible from this test? I think that the ringing frequency is a function of stray capacitance and stray inductance. Thank you in advance.

[@Nexperia]

Hello, thanks for your questions! 1) Inductor size does not matter very much, it just needs to be large enough to act as a constant current source between the switching intervals and it can be representative of the inductor in the application at hand. The charging time is related to the inductor size. 2) It can be approximated from the waveforms as the dip in the Vds @ turn on is directly related to the loop inductance and the di/dt (approximation and dependent on where it is measured Vds dip = L_loop * di/dt). Ringing frequency is related to the parasitic inductance and capacitance in the circuit and is damped by the resistance in the circuit. • Also, Snubbers are a good way to damp oscitations. (Check the this application note: assets.nexperia.com/documents/application-note/AN11160.pdf) • Also, check the application note (Half-bridge MOSFET switching and its impact on EMC) assets.nexperia.com/documents/application-note/AN90011.pdf

[@AnkitPal-ls3tz]

thank you for the video , i have the doubt regarding the turn off time duration t2 . for t1 duration its (Lload*Itest)/Vdc , mainly less than 100us . what should be the formula or trick behind t2 pulse duration ?

[@Nexperia]

The aim behind the turn OFF period (t2 as mentioned) is to properly allow the device to be turned off. The period may be several times larger than the devices turn OFF time. When it comes to the 2nd pulse, its aim is to properly turn ON the device but at the same time it's duration could be quite short to keep the current low, this will avoid possible damage to the device or inductor saturation. In this case the period should be a minimum of several times bigger than the device's turn on time. Thanks for watching!