Lecture 10: Interrupt Enable and Interrupt Priority

[@pablom695]

I can only imagine how good the book would be with such smart and immaginative bvideos. Will buy them for work ,thanks Mr Zhu!

[@embeddedsystemswitharmcort9051]

My pleasure!

[@Graham1904]

Great video/tutorial, it's a shame that the commentary is computerised speech!

[@dexterrik]

4:14 ICER stands for Interrupt Clear Enable Register

[@embeddedsystemswitharmcort9051]

Thanks.

[@kingfalconkhan]

Great video but I have two questions: 1. At 9:43, isn't it supposed to be: each register holds 4 priority 'bits' ? 2. At 11:25, isn't it supposed to be just 5 as you said (as 5

[@embeddedsystemswitharmcort9051]

(1) No. Each register has 32 bits, consists of 4 priority bytes. (2) No. Bits 0:3 in the BASEPRI registers are reserved. We can only modify the values of bits 7:4.

[@rashadshubita1941]

Excellent thank you! but why I found a priority more than 15 in the datasheet of stm32f103c8t6 even that run in cortex-m3, that implements a "(4 bits of interrupt priority are used)" ?

[@embeddedsystemswitharmcort9051]

The most significant four bits are used for priority. For STM32L4L4, the priority register value should be 15

[@coderhex1675]

4:25 to enable interrupt 44 -> to disable interrupt 44

[@pavanreddy6088]

Excellent

[@MrPatrick5333]

Excellent

[@zach_stow]

Excellent

[@OverlordNibble]

Excellent

[@ahmetyldz5674]

How can i buy your book as e-book? Amazon doesnt delivery to my country.

[@embeddedsystemswitharmcort9051]

Sorry. No e-book yet.

[@krish2nasa]

Excellent

[@khaledhumood7987]

why only 2 dislikes???

[@ManchesterBlackSheep]

Oh the voice. Unwatchable.