Episode #72: Quantum tunneling, and nanomaterials for energy storage

[@timlinn3149]

What are some implications/differences in testing EIS in a 2-electrode configuration (WE - RE/CE) compared to an external reference electrode, 3 configuration? If the application relies on a two-electrode configuration it makes sense to test EIS in this way, but I would not want to miss something significant.

[@Pineresearch]

This is a great question. Essentially, the main difference is with what you are physically measuring. With a 2-electrode configuration, your EIS spectra contain the response at BOTH the working and counter electrodes. However, with a 3-electrode configuration, your EIS spectra ONLY contain the response of the working electrode. This is why, for example, when you see battery EIS data (which are almost always collected in a 2-electrode anode/cathode setup) you routinely see explanations of which portion corresponds to the anode, and which to the cathode. Conversely, when studying a 3-electrode setup and its EIS data, the results are only pertaining to the working electrode. The counter electrode does not factor into the data. The main reason for this is probably a bit more complicated than can be concisely explained in a comment here (and, frankly, it is fairly complex electrical engineering related to potentiostat design and operation that may be a little beyond my ability to explain), but basically it is because with a 2-electrode setup the counter electrode is exactly equal and opposite in E/i to the working electrode. With a 3-electrode setup, due to the presence of the reference electrode and separation of the high impedance reference sense line from the low impedance counter drive line, the counter electrode is not always exactly equal and opposite to the working. Mainly though, I would just focus on the practical result I mentioned initially: 2-electrode = both are contained in the data; 3-electrode = only the working.

[@vidzajaknap7726]

Hello guys, I’m analyzing EIS data collected around OCP on Titanium alloys and amorphous Ti-based TFMGs to study corrosion resistance. My measurements show two capacitive loops: the first, from 100 to 1 Hz, remains stable around -80° over 1 to 168 hours, and the second, from 0.1 to 0.01 Hz, becomes more capacitive over time (phase angle shifts from -65° to -80°). Which of these loops is likely to represent the space charge region, and which one represents the barrier layer? Any insights would be appreciated!

[@Pineresearch]

Very good and detailed question! Of course, the caveats I must give for my answer are that I am not seeing your data personally, and I cannot be perfectly certain having not worked extensively with Ti, Ti-alloys, TFMGs, etc. myself. That being said, my educated guess is that the capacitive loop that remains relatively unchanged would correspond to the space-charge region, while the one that changes over time would correspond to any film/passivation/barrier layer. My reasoning behind this is that the space-charge region is an intrinsic property of a semiconductor, and while I suppose something could change with the material over a week of testing, I might expect it to remain mostly the same if you are using the same potential (OCP) throughout the duration. However, it is much more feasible to me that any passivation or barrier layer could change over time - think about it like the diffusion layer thickness, which can grow steadily over time. I think it far more likely that a film may develop and/or grow over the course of time, which might lead to greater degree of capacitive response as you are observing.

[@vidzajaknap7726]

Thank you for your reply! I was actually thinking along the same lines but wasn’t completely sure, so your perspective really helps. I’d love to share some Bode diagrams, but I didn’t want to burden you with more of my research data. Thanks again for your insights!