From top to Transistors: opensource Verilog to ASIC flow

Go from HDL to physical CMOS layout right now with open-source tools, by following this HOWTO guide and demo. When things go well, the design can be converted to GDS for ASIC fabrication in a single step. I also show how we can dig deeper, using yosys, openlane and openroad, when the hardening processes isn't quite as simple.
This is part of my journey through the zero to ASIC course, so I don't have all the answers, but have found some interesting bits already. Let me know if you see mistakes, or have hints! I'll be updating the ASIC playlist with more as I progress.
** Links of interest **
Details, written instructions, downloads:
inductive-kickback.com/2023/0...
My fork of the demo structure, with the Makefile used in the video:
github.com/psychogenic/tt03-v...
OpenLane:
github.com/The-OpenROAD-Proje...
TinyTapeout:
tinytapeout.com/

[@gabrielbarrientos468]

Man! Great videos!!! The way you explain the workflow and the different levels of abstraction is just so cool!

[@PsychogenicTechnologies]

Gabriel, thanks so much! I've been trying to find the right balance to hit the sweet spot between just the juicy bits and all the details, so a bit of feedback on what's good/isn't helps a lot. Thanks again :)

[@ngeren]

Pat! You're a natural!

[@runforitman]

Very much appreciate this Im trying to go from FPGA to ASIC and found the software overwhelming But your videos are really helpful in giving me a sense of direction

[@PsychogenicTechnologies]

That's great to hear, thanks!!

[@amop2250]

Great video! Both entertaining AND informative!?

[@PsychogenicTechnologies]

That's great to hear: what I hope for when having fun learning cool stuff. Thanks!

[@AfricanBushmechanic]

I have never been i college but am taking a VLSI Cad course on Coursera . I don't want to learn python, My question is how do i generate an ASCII format file with Verilog(.v). I know how to upload .v to FPGA but am confused on how to generate an ASCII file.

[@AfricanBushmechanic]

Thanks for your video. Is it possible for your pictures back ground to be invisible it's hidden some words that you are typing.

[@maesitos]

I cracked up with the opening

[@PsychogenicTechnologies]

ah, Guillermo: so I'm *not* the only one? hah! Thanks for letting me know :) I hope the info is a good as the lulz.

[@CalvBore]

Hey, awesome video! was really neat to see you work through some of the errors that openlane was giving you. I just found openlane a few days ago. Would be really cool to see you g through the flow with openlane2! Have you managed to make any designs that incorporated analog components? I think it'd be super interesting to get a PUF into a design. Would love to see more openlane videos from you!

[@PsychogenicTechnologies]

Hello Calvin, thanks! I haven't played with the latest openlane stuff and have been itching to, so yeah... both that and doing some ASIC analog are on my wishlist/plan--so I'll make sure to document and share. Right this minute I'm focused on getting one or two projects in for TinyTapeout 5, which is coming soon, and prepping to go to supercon (to do more tinytapeout stuff and to hopefully upgrade through osmosis just by hanging around all the cool peeps that'll be there). Back from that, will be turning to editing the giant stack of queued videos, and then finally playing with new stuff! Thanks again for the feedback. Cheers!

[@JohnathanSammer]

thats quite amazing - how many bits was the frequency counter and how fast could it clock itself.

[@PsychogenicTechnologies]

Hi Johnathan! I can't actually remember number of bits at this point, but since I based my neptune thing on the idea of frequency counting and reused what I could, I probably had done something like github.com/psychogenic/neptune/blob/main/neptune/pulsecounter.py -- in short, giving myself enough bits for whatever the max count would be automatically. As for speed, internally the sky130 process can handle into the GHz so the limiting factor is basically I/O. Back in the days of TT03, this was a sad something kHz. By now, the I/O is rated with a bandwidth of 50MHz, but for inputs you can actually go at least 10s of MHz higher than that (tested it up to 70 but am pretty sure someone in the discord had made it close to 100 or so before seeing junk). Finally, you've got the edge detection crossing clock domains, so wind up using a flip flop synchronizer--it's parametric, but I've basically always used only two stages at this point, which (I think) implies that you'll hit a wall for pulses coming in faster than half the clock rate

[@maylermartins]

Hi, nice video! About the congestion, you can get the instance name in the congested area and do a grep in the mapped verilog. That you give +- an idea what module (and surroundings) are congested. Usually cells from the same module are placed together. However, I am not sure what is the strategy for the name composition in the physical synthesis. I would guess module_name_inst_name.

[@PsychogenicTechnologies]

Hello Mayler--thanks! So poking around following your suggestion, I found that in the run under results/final/verilog/gl there are two .v files, one name.v and the other name.nl.v (one is powered, the other not, so the only differences are connections to vssd1 and vccd1). The naming is pretty awful ... just _number_ so there are things like sky130_fd_sc_hd__and2_1 _384_ (.A(_079_), .B(_168_), .X(_169_)); strewn about. However, that example was just a worse case. The wires, here, are from stuff nearby in the file and naming coming from my own modules is peppered throughout. So just above AND gate 384, there, is some AND-NOR that's providing input B of the AND, and that pretty much tells me where this stuff is from sky130_fd_sc_hd__a22o_1 _383_ (.A1(\counterfsm.display_valueUnits[0] ), .A2(_158_), .B1(_159_), .B2(\counterfsm.runningCount[0] ), .X(_168_)); So you were right... a little more "manual" than I'd hope, but at least it's possible to get an idea where all that is happening. Gracias!

[@maylermartins]

@@PsychogenicTechnologies yes, the naming conventions shown are pretty ugly. Nets use double underlines and instances use just one. Super confusing indeed.

[@maylermartins]

The other verilog exposes the pg (power ground) pins, both will implement the same logic.

[@PsychogenicTechnologies]

@@maylermartins uuf, yes... I hadn't noticed the difference. Still dealing with a bit of overwhelm as this subject goes so deep, details under details, never seem to hit the bottom (turtles all the way down, heh). Nice to find that there are lots of people, like you, who know more and are happy to share. Thanks :)

[@user-ht4mo5cx8d]

Hello, I'm really interested in this topic overall but I don't know where to get started (I'm trying to figure out whether this is a career I want to pursue) Any help would be greatly appreciated Some background on me : I'm currently a third year computer engineering student and I'm trying to find if software or hardware fits me more Thanks again!

[@PsychogenicTechnologies]

I say try before you buy :) The good news with all this is that it's now so accessible: you have a computer, you're all set thanks to the open ecosystem that has sprung up. I don't know about you, but one of the quickest ways I learn anything is to have some goal in mind and get what I need to accomplish it. With ASICs, the well runs very deep--you could spend your life exploring it. My recommendation is to start close to where you are now, focusing on the two things you need to acquire: some tooling, of course, but mostly a bit of a shift in mindset. If you want to break it into two parts, which I'd recommend, you can focus on the *mindset* by leveraging what you already know to start. You can use Python (Amaranth) and an inexpensive FPGA module and start on a small project where you get a flavour for the difference between writing an algorithm vs describing hardware. If that's fun, then you can either move to verilog, or stick with Python and deepen the complexity of your projects. Get into cryptography, or image processing or whatever interests you that gets hard fast. If you like CPUs, check out the "LMARV-1 reboot" playlist (and others) from Robert Baruch. Either way, if you are doing digital design, there is little difference between designing for FPGAs or ASICs, so you'll be ready to do TinyTapeout runs very fast. Worst case is that you got to sculpt some atoms and did something that was near impossible only a few years ago. And who knows, maybe it will turn into a career. Good luck and have fun.

[@modernsolutions6631]

Gosh you look amazing. What routines of yours/things you do would you say are most responsible for your good looks? sorry for the odd question. I didn't have a had a dad who taught me how to look like i care about myself.

[@PsychogenicTechnologies]

Hi! First off: thank you--that's a generous compliment, especially assuming I have anything to do with it. But ok, this is not my customary topic area but I hear where you're coming from and appreciate a straightforward question so will give it a shot. I have been interested in the question myself and, assuming there is something I do that actually plays a positive role and counterbalances all my awful habits, it can only boil down to 3 things: 1) Years ago, a younger sibling asked me "hey, is milk actually good for you?" I was about to answer and realized... I actually knew nothing beyond what had been injected to me via marketing as a child. So I did some research, that lead to lots more, that lead to changing everything I eat. The videos on nutritionfacts.org/ are precious. 2) Functional fitness: nothing refreshes the bod or gives more glow than feeling good and being physically effective. That and carrots, I guess. But when I do move, I do HIIT training at home and it pays back in spades. 3) Autophagosomes and mitochondrial management. I think that started when I took this short course: www.edx.org/learn/physiology/tokyo-institute-of-technology-autophagy-research-behind-the-2016-nobel-prize-in-physiology-or-medicine Pretty mindblowing actually. But short version is hot/cold exposure for mitochondrial refresh on exposed bits and intermittent fasting for everything on the inside. Finally, you have to realize that, on top of being a subjective impression, there is movie magic involved. I use decent lighting and such, but also there are days/whole periods when I'm just not vibbing, feel and look like crap, and can't bring myself to face the camera. So, I'll record some PCB or scope results or whatever and figure I'll do the discussion part on a better day. This is one way I wind up with a giant stack of TODO videos, and you only see me on "good days". I don't know if this helps, but you asked and that's my story. Hope you have some nice holidays and an awesome 2024 :)

[@PsychogenicTechnologies]

Oh, and thinking of this I realize I only addressed the purely physical--which is fundamental/necessary, but not sufficient. I think presence and the impression we leave are based on behaviour, big time... you know, body language and tone of voice and all that. It's an interesting area, and I'm sure it can be worked on, but I sidestep all that with two things: 1) remembering we're all doing our best and, when you round it off, none of us knows anything really... so I try hard and refuse to worry about the rest and just... relax 2) I only talk about things I care about/find fascinating, and think I can give to others. I think those two things get you confidence and a pretty good vibe: the excitement spreads and, just by the halo effect, you tend to look shinier for free. Anyhow... that, I think, definitely concludes my thoughts on the subject. Cheers!

[@tombouie]

Thks buts ?why do all the super-smart open-source folks have super long hair?. Hmmmmmmm ....... sooooooooo ....... if I grow super long hair, ....... I justs-mights gets-smarts too ;)

[@PsychogenicTechnologies]

hahah! I don't know if it applies to all, or even to me, but I does seem to be that most of my strengths, including IQ, are held in keratin... kind of a weakness, really, so don't let the word get out! lol

[@NotAnInterestingPerson]

Well I’m screwed, then 😂